Solid-state image sensing apparatus, control method, and electronic device

Patent metadata

Field	Value
Publication number	US-10630930-B2
Application number	US-201916439567-A
Country	US
Kind code	B2
Filing date	Jun 12, 2019
Priority date	Dec 15, 2014
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

The present disclosure relates to a solid-state image sensing apparatus, a control method, and an electronic device capable of reducing a settling time of a vertical signal line at the time of a read operation of pixels. A column processing unit A/D converts pixel signals of a plurality of pixels. A vertical signal line feeds the pixel signals output from the pixels to the A/D converter. A pull-up circuit increases a potential of the vertical signal line at the time of starting a read operation of the pixels. For example, the present disclosure can be applied to a CMOS (Complementary Metal-Oxide Semiconductor) image sensor that performs an interleaving operation or the like.

First claim

The invention claimed is:

1. An imaging device comprising:
a first pixel including a first photoelectric converter and a first plurality of transistors;
a first signal line coupled to the first pixel;
a first current source coupled to the first signal line; and
a first transistor and a second transistor connected in series between the first signal line and a fixed potential, wherein the first transistor receives a control signal and functions as a switch and wherein the second transistor receives a predetermined potential and functions as a comparator to increase a potential of the first signal line when the potential of the first signal line is less than the predetermined potential.

2. The imaging device comprising according to claim 1 , further comprising:
a second pixel including a second photoelectric converter and a second plurality of transistors;
a third signal line coupled to the second pixel;
a fourth signal line coupled to the third signal line;
a second current source coupled to the fourth signal line;
a second comparator coupled to the third signal line;
a third transistor and a fourth transistor between the second signal line and the fixed potential.

3. The imaging device comprising according to claim 2 , further comprising a fifth transistor coupled to the second signal line and the fourth signal line.

4. The imaging device comprising according to claim 2 , wherein the third transistor and the fourth transistor are connected in series.

Assignees

• Sony Corp

Inventors

• Matsumoto Shizunori
• Moyade Pawankumar Pradeepkumar

Classifications

• H04N25/616 Primary

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N5/378 Primary

  Electricity · mapped topic

• H04N5/3456

  Electricity · mapped topic

• H04N5/3575

  Electricity · mapped topic

• H04N5/3745

  Electricity · mapped topic