Image forming apparatus incorporating control circuitry for executing control method to arbitrate access between signals referring priority settings

Patent metadata

Field	Value
Publication number	US-10630865-B2
Application number	US-201916390392-A
Country	US
Kind code	B2
Filing date	Apr 22, 2019
Priority date	Jun 18, 2018
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

Control circuitry includes a converter and an arbitration unit. The converter is configured to convert a first signal based on a first communication standard to an internal second signal based on a second communication standard and output the internal second signal. The arbitration unit is configured to arbitrate between access of the internal second signal output from the converter and access of an external second signal, which is also based on the second communication standard, input from outside the control circuitry.

First claim

What is claimed is:

1. Control circuitry incorporated into an image forming apparatus comprising:
an interface controller configured to receive a first signal, the interface controller including a converter configured to convert the first signal based on a first communication standard into an internal second signal based on a second communication standard and output the internal second signal;
a central processing unit (CPU) interface including an arbitration unit, the CPU interface being configured to receive the internal second signal from the converter and an external second signal from outside the control circuitry, the external second signal being based on the second communication standard, the arbitration unit being configured to arbitrate between access of the internal second signal and access of the external second signal;
a communication buffer configured to receive an input of the first signal and an input of the external second signal; and
an interrupt controller configured to:
output an interrupt signal in response to the input of the first signal to the communication buffer, to a second CPU configured to output the external second signal; and
output an interrupt signal in response to the input of the external second signal to the communication buffer, to a first CPU configured to output the first signal.

2. The control circuitry according to claim 1 , further comprising a setting register, in which an arbitration rule of the arbitration unit is set, included in the CPU interface.

3. The control circuitry according to claim 2 ,
wherein priority between the access of the internal second signal output from the converter and the access of the external second signal input from outside the control circuitry is set in the setting register.

4. The control circuitry according to claim 1 , further comprising a register configured to be read and written by the CPU interface,
wherein the CPU interface is configured to receive an input of a signal in response to the interrupt signal from the second CPU and determine if access of the second CPU is allowable,
wherein the CPU interface is configured to read from and write to the register according to the signal input from the second CPU when the access of the second CPU is allowable,
wherein the interface controller is configured to receive an input of a signal in response to the interrupt signal from the first CPU and determine if access of the first CPU is allowable, and
wherein the converter is configured to convert the first signal input from the first CPU into the internal second signal and output the internal second signal to the CPU interface when the access of the first CPU is allowable.

5. The control circuitry according to claim 1 ,
wherein the interface controller determines if the first signal is an unauthorized input and notifies the first CPU of an error in case of the unauthorized input.

6. The control circuitry according to claim 1 ,
wherein the first communication standard is a peripheral component interconnect (PCI) express standard, and
wherein the interrupt controller is configured to output the interrupt signal to the first CPU as a packet based on the first communication standard.

7. The control circuitry according to claim 1 ,
wherein the interface controller is configured to determine if the second CPU is connected to the CPU interface in response to the input of the first signal.

8. The control circuitry according to claim 1 , further comprising:
a scanner image processor configured to perform image processing on image data read by a scanner; and
a plotter image processor configured to perform image processing on image data output from a plotter.

9. An image forming apparatus comprising:
the control circuitry according to claim 8 ;
the scanner configured to read an image and create the image data; and
the plotter configured to form an image on a recording medium based on the image data.

10. A control method to be executed by control circuitry including a converter, an arbitration unit, a communication buffer, and an interrupt controller, the method comprising:
converting, by the converter, a first signal based on a first communication standard into an internal second signal based on a second communication standard and outputting the internal second signal;
arbitrating, by the arbitration unit, between access of the internal second signal converted from the first signal and access of an external second signal, which is also based on the second communication standard, input from outside the control circuitry;
in response that the first signal being input to the communication buffer; outputting, by the interrupt controller, an interrupt signal to a second central processing unit (CPU) configured to output the external second signal; and
in response that the external second signal being input to the communication buffer, outputting, by the interrupt controller, an interrupt signal to a first CPU configured to output the first signal.

Assignees

• Watanabe Yuuto
• Ricoh Co Ltd

Inventors

• Watanabe Yuuto

Classifications

• H04N1/00854

  Recognising an unauthorised user or user-associated action · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• H04N1/32582

  Output interface · CPC title

• H04N1/00856

  Preventive measures · CPC title

• G06F13/26 Primary

  with priority control · CPC title