Semiconductor device with cell trench structures and recessed contacts and method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-10629676-B2
Application number	US-201816110508-A
Country	US
Kind code	B2
Filing date	Aug 23, 2018
Priority date	Aug 9, 2013
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a plurality of source zones of a first conductivity type formed in a semiconductor substrate as stripes which extend lengthwise in parallel in a first direction;
a plurality of body zones of a second conductivity type opposite the first conductivity type formed in the semiconductor substrate below the plurality of source zones;
a plurality of heavily doped contact zones formed in the body zones;
a plurality of first cell trench structures formed in the semiconductor substrate and extending lengthwise in parallel in a second direction transverse to the first direction so as to transect the stripes of source zones and the body zones, each first cell trench structure comprising a first buried electrode and a first insulator layer between the first buried electrode and the semiconductor substrate;
a plurality of second cell trench structures formed in the semiconductor substrate and extending lengthwise in parallel in the second direction so as to transect the stripes of source zones and the body zones, two or more first cell trench structures of the plurality of first cell trench structures being interposed between neighboring ones of the second cell trench structures, each second cell trench structure comprising a second buried electrode and a second insulator layer between the second buried electrode and the semiconductor substrate;
a recess formed in the first insulator layer along a sidewall of one or more of the first cell trench structures and vertically extending to the corresponding heavily doped contact zone; and
an electrically conductive material disposed in each recess formed in the first insulator layer and contacting the corresponding first buried electrode, the corresponding source zone and the corresponding heavily doped contact zone at the sidewall.

2. The semiconductor device of claim 1 , wherein the sidewall of the one or more first cell trench structures with the recess is tilted by less than 90 degrees with respect to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

3. The semiconductor device of claim 1 , wherein the first insulator layer has a uniform width.

4. The semiconductor device of claim 1 , wherein the width of each recess increases with increasing proximity to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

5. The semiconductor device of claim 1 , wherein the width of the first buried electrode in each first cell trench structure with a recessed first insulator layer decreases with increasing proximity to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

6. The semiconductor device of claim 5 , wherein the width of the first buried electrode in each first cell trench structure with a recessed first insulator layer is generally uniform below the recess.

7. The semiconductor device of claim 1 , further comprising a capping layer formed on a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend, wherein the electrically conductive material disposed in each recess formed in the first insulator layer extends through openings in the capping layer to form part of an overlying contact structure.

8. The semiconductor device of claim 7 , wherein the first buried electrode of one or more of the first cell trench structures is electrically contacted by the contact structure through an additional opening in the capping layer which is aligned with a top side of the first buried electrode.

9. The semiconductor device of claim 1 , wherein the first buried electrodes are electrically coupled to a source potential, and wherein the second buried electrodes are electrically coupled to a gate potential.

10. The semiconductor device of claim 1 , wherein the semiconductor device is an IGBT.

11. The semiconductor device of claim 1 , wherein between neighboring ones of the stripes of source zones stripes, the body zones extend to a first main surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures extend.

12. The semiconductor device of claim 1 , wherein interfaces between the source zones and the body zones run approximately parallel to a first surface of the semiconductor substrate into which the plurality of first cell trench structures and the plurality of second cell trench structures at a first distance, wherein a second distance between the first surface and an edge of the electrically conductive material at a bottom of each recess formed in the first insulator layer is greater than the first distance, wherein interfaces between the body zones and a drift layer of the first conductivity type run approximately parallel to the first surface at a third distance, and wherein the second distance is smaller than the third distance.

13. The semiconductor device of claim 1 , wherein between first cell trench structures of the plurality of first cell trench structures for which the first buried electrode is contacted by the electrically conductive material through the recess formed in the corresponding first insulator layer, the buried electrode of at least one first cell trench structure of the plurality of first cell trench structures is contacted by the electrically conductive material only at a first main surface of the semiconductor substrate.

14. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of source zones of a first conductivity type in a semiconductor substrate as stripes which extend lengthwise in parallel in a first direction;
forming a plurality of body zones of a second conductivity type opposite the first conductivity type in the semiconductor substrate below the plurality of source zones;
forming a plurality of heavily doped contact zones in the body zones;
forming a plurality of first cell trench structures in the semiconductor substrate and extending lengthwise in parallel in a second direction transverse to the first direction so as to transect the stripes of source zones and the body zones, each first cell trench structure comprising a first buried electrode and a first insulator layer between the first buried electrode and the semiconductor substrate;
forming a plurality of second cell trench structures in the semiconductor substrate and extending lengthwise in parallel in the second direction so as to transect the stripes of source zones and the body zones, two or more first cell trench structures of the plurality of first cell trench structures being interposed between neighboring ones of the second cell trench structures, each second cell trench structure comprising a second buried electrode and a second insulator layer between the second buried electrode and the semiconductor substrate;
forming a recess in the first insulator layer along a sidewall of one or more of the first cell trench structures and vertically extending to the corresponding heavily doped contact zone; and
disposing an electrically conductive material in each recess formed in the first insulator layer so as to contact the corresponding first buried electrode, the corresponding source zone and the corresponding heavily doped contact zone at the sidewall.

15. The method of

Assignees

• Infineon Technologies Ag

Inventors

• Laven Johannes Georg
• Cotorogea Maria
• Schulze Hans-Joachim
• Itani Haybat
• Griebl Erich
• Haghofer Andreas

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P32/1204

  from a plasma phase · CPC title

• H10P32/00

  Diffusion of dopants within, into or out of wafers, substrates or parts of devices (during formation of materials H10P14/00) · CPC title

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title