Three dimensional semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-10629609-B2
Application number	US-201715722485-A
Country	US
Kind code	B2
Filing date	Oct 2, 2017
Priority date	Mar 9, 2017
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

First claim

What is claimed is:

1. A three-dimensional semiconductor device, comprising:
a substrate including a first area and a second area, the first area and the second area horizontally adjacent to each other in a first direction;
a first gate electrode and a second gate electrode, sequentially stacked on the first area of the substrate and extending parallel to a surface of the substrate and in the first direction from the first area to the second area, each of the first gate electrode and the second gate electrode including a first cell gate portion disposed on the first area and formed continuously in a horizontal, second direction perpendicular to the first direction, and including a first gate extension portion and a second gate extension portion extended from the first cell gate portion in the first direction and horizontally separated from each other in the second direction, the first gate electrode including a first pad portion, and the second gate electrode including a second pad portion; and
channel structures disposed in the first area of the substrate and penetrating through the first gate electrode and the second gate electrode,
wherein the first pad portion of the first gate electrode is disposed on an end portion of the first gate extension portion of the first gate electrode and the first pad portion protrudes, with respect to the first gate extension portion, in a third, vertical, direction,
wherein the second pad portion of the second gate electrode is disposed on an end portion of the second gate extension portion of the second gate electrode and the second pad portion protrudes, with respect to the second gate extension portion, in the third direction, and
wherein the second gate electrode includes a protruding portion disposed on an end portion of the first gate extension portion of the second gate electrode, wherein the protruding portion protrudes, with respect to the first gate extension portion, in the third direction, and has a different horizontal width in the second direction from the second pad portion.

2. The three-dimensional semiconductor device of claim 1 , wherein the second pad portion and the protruding portion have the same maximum thickness in the third direction.

3. The three-dimensional semiconductor device of claim 1 , wherein the width of the second pad portion in the second direction is greater than the width of the protruding portion in the second direction.

4. The three-dimensional semiconductor device of claim 1 , wherein the protruding portion of the second gate electrode vertically overlaps the first gate extension portion of the first gate electrode.

5. The three-dimensional semiconductor device of claim 1 , wherein the second pad portion does not vertically overlap the first pad portion or any other pad portion of the first or second gate electrode.

6. The three-dimensional semiconductor device of claim 1 , wherein each of the first gate electrode and the second gate electrode comprises a second cell gate portion disposed on the first area and disposed to be horizontally spaced apart from the first cell gate portion in the second direction, a third gate extension portion and a fourth gate extension portion, extended from the second cell gate portion in the first direction and horizontally spaced apart from each other in the second direction, and a gate connection portion connecting the first cell gate portion and the second cell gate portion to the first gate extension portion, the second gate extension portion, the third gate extension portion, and the fourth gate extension portion, and
wherein the first gate extension portion, the second gate extension portion, the third gate extension portion, and the fourth gate extension portion are sequentially arranged in the second direction.

7. The three-dimensional semiconductor device of claim 6 , further comprising:
a third gate electrode on the second gate electrode; and
a fourth gate electrode on the third gate electrode,
wherein each of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode includes the first cell gate portion, the second cell gate portion, the first gate extension portion, the second gate extension portion, the third gate extension portion, the fourth gate extension portion, and the gate connection portion.

8. The three-dimensional semiconductor device of claim 7 , wherein the third gate electrode comprises a third pad portion disposed on an end portion of the third gate extension portion of the third gate electrode, and the third pad portion protrudes, with respect to the third gate extension portion, in the third direction,
wherein the fourth gate electrode comprises a fourth pad portion disposed on an end portion of the fourth gate extension portion of the fourth gate electrode, and the fourth pad portion protrudes, with respect to the fourth gate extension portion, in the third direction, and
wherein at least one of the first pad portion, the second pad portion, the third pad portion, and the fourth pad portion vertically overlap at least one gate extension portion of a different gate electrode, but none of the first pad portion, the second pad portion, the third pad portion, and the fourth pad portion vertically overlap any other pad portion of the first gate electrode, second gate electrode, third gate electrode, or fourth gate electrode.

9. The three-dimensional semiconductor device of claim 8 , wherein the third gate electrode comprises a protruding portion disposed on an end portion of the second gate extension portion of the third gate electrode, wherein the protruding portion protrudes, with respect to the second gate extension portion of the third gate electrode, in the third direction, and
wherein the fourth gate electrode comprises a protruding portion disposed on an end portion of the third gate extension portion of the fourth gate electrode, wherein the protruding portion protrudes, with respect to the third gate extension portion of the fourth gate electrode, in the third direction.

10. The three-dimensional semiconductor device of claim 4 , wherein the first gate extension portion of the first gate electrode is below and vertically overlaps the protruding portion of the second gate electrode and includes the first pad portion.

11. The three-dimensional semiconductor device of claim 6 , wherein for each of the first gate electrode and the second gate electrode, only one of the first gate extension portion, the second gate extension portion, the third gate extension portion, and the fourth gate extension portion include a pad portion formed thereon.

12. The three-dimensional semiconductor device of claim 6 , wherein the first gate electrode is between the substrate and the second gate electrode, and the second gate extension portion of the first gate electrode extends the same distance in the first direction as the second gate extension portion of the second gate electrode on which the second pad portion is formed.

13. The three-dimensional semiconductor device of claim 7 , wherein for at least one of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode, at least one gate extension portion extends further in the first direction that at least another gate extension portion.

14. A three-dimensional semiconductor device, comprising:
a substrate including a first area and a second area, the first area and the second area horizontally adjacent to each other in a first direction;
a first gate electrode and a second gate electrode, sequentially stacked on the first area of the substrate and extending parallel

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Chang Sup
• Nam Phil Ouk
• Lee Sung Yun
• Kang Chang Seok

Classifications

• H01L23/5226

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L23/53295

  Electricity · mapped topic

• H01L27/11548

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic