Liquid crystal display device and driving method thereof

Patent metadata

Field	Value
Publication number	US-10629146-B2
Application number	US-15370708-A
Country	US
Kind code	B2
Filing date	May 22, 2008
Priority date	May 29, 2007
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A liquid crystal display (LCD) device and a driving method where the LCD device includes a data controller for interleaving one of black gray scale data and intermediate gray scale data into input digital video data to input digital video data in a specific period preceding a second one of two successive frame periods in which data voltages having the same polarity are successively supplied to liquid crystal cells. A timing signal controller generates a data timing signal and a gate timing signal, based on an input timing signal, and accelerates a frequency of the data timing signal and a frequency of the gate timing signal in the specific period. A data driving circuit is included for converting the interleaved digital video data into an analog voltage in response to the data timing signal, and supplying the analog voltage to data lines in the specific period.

First claim

What is claimed is:

1. A liquid crystal display device comprising:
a liquid crystal display panel formed with a plurality of data lines and a plurality of gate rows, the liquid crystal display panel having a plurality of liquid crystal cells;
a data controller for interleaving one of black data and intermediate gray data that is between the black data and white data with first input digital video data in a period preceding a second one of two successive frame periods of a plurality of frame periods;
a timing signal controller generating a data timing signal and a gate timing signal, and accelerating a frequency of the data timing signal and a frequency of the gate timing signal in the period preceding the second one of the two successive frame periods by a multiple of (i+1)/i, where i is a portion of gate rows of the liquid crystal display panel that is enabled;
a data driving circuit converting the first input digital video data interleaved with the black data or the intermediate gray data into first analog data voltages and one of black data voltages and intermediate gray data voltages in response to the accelerated frequency of the data timing signal, and supplying the first analog data voltages to the plurality of data lines in the period preceding the second one of the two successive frame periods, and converting second input digital video data not interleaved with the black data or the intermediate gray data into second analog data voltages in response to the frequency of the data timing signal, which is not accelerated, and supplying the second analog data voltages to the plurality of data lines in a part of the plurality of frame periods that excludes the period preceding the second one of the two successive frame periods; and
a gate driving circuit including a plurality of gate integrated circuits operating independently, the plurality of gate integrated circuits supplying a plurality of scan pulses to the plurality of gate rows, one gate integrated circuit supplying scan pulses to i number of gate rows to which first analog data voltages are supplied to the plurality of liquid crystal cells and another gate integrated circuit supplying scan pulses to another i number of gate rows to which one of black data voltages and intermediate gray data voltages are supplied to the plurality of liquid crystal cells in the period preceding the second one of the two successive frame periods in response to the accelerated frequency of the gate timing signal, and the plurality of gate integrated circuits supplying the plurality of scan pulses to the plurality of gate rows in the part of the plurality of frame periods that excludes the period preceding the second one of the two successive frame periods in response to the frequency of the gate timing signal, which is not accelerated,
wherein the second analog data voltages are inverted in polarity in every frame of the part of the plurality of frame periods that excludes the period preceding the second one of the two successive frame periods.

2. The liquid crystal display device according to claim 1 , wherein the accelerated frequency of the gate timing signal further comprises a gate start pulse instructing output start points of the plurality of gate integrated circuits, the gate start pulse being generated to have one horizontal period pulse width of a plurality of horizontal period pulse widths in the period preceding the second one of the two successive frame periods.

3. The liquid crystal display device according to claim 2 , wherein the gate timing signal comprises a plurality of gate output enable signals, and the gate output enable signals are generated to periodically have the one horizontal period pulse width of the plurality of horizontal period pulse widths, and are supplied to the plurality of gate integrated circuits after being sequentially shifted, respectively.

Assignees

• Song Hong Sung
• Min Woong Ki
• Jang Su Hyuk
• Lg Display Co Ltd

Inventors

• Song Hong Sung
• Min Woong Ki
• Jang Su Hyuk

Classifications

• G09G3/3614

  Control of polarity reversal in general · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2320/0257

  Reduction of after-image effects · CPC title

• G09G2310/061

  for resetting or blanking · CPC title