Back power protection (BPP) in a system on a chip (SOC) with critical signaling scheme

Patent metadata

Field	Value
Publication number	US-10627881-B2
Application number	US-201815952071-A
Country	US
Kind code	B2
Filing date	Apr 12, 2018
Priority date	Apr 12, 2018
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

Aspects of the disclosure are directed to a System on a Chip (SOC). In accordance with one aspect, a method for implementing back power protection (BPP) in a SOC includes transmitting a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function; transmitting a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function; using the logical OR function to generate a composite BPP power based on the first BPP supply output and the second BPP supply output; and inputting the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.

First claim

What is claimed is:

1. A method for implementing back power protection (BPP) in a System on a Chip (SOC), the method comprising:
transmitting a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function;
transmitting a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function;
using the logical OR function to generate a composite BPP power based on the first BPP supply output and the second BPP supply output; and
inputting the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.

2. The method of claim 1 , wherein the first PMIC is coupled to an application processor (AP) and wherein the application processor (AP) serves as a master processor.

3. The method of claim 2 , wherein the second PMIC is coupled to the baseband processor (BP) and wherein the baseband processor (BP) serves as a communications processor.

4. The method of claim 3 , wherein the application processor (AP) and the baseband processor (BP) are both coupled to a common multi-drop data bus in the SOC.

5. The method of claim 4 , further comprising generating a time-critical alert signal based on a back power protection (BPP) input signal to the baseband processor (BP).

6. The method of claim 5 , wherein the back power protection (BPP) input signal is the composite BPP power.

7. The method of claim 5 , further comprising transmitting the time-critical alert signal to at least one of the first PMIC and the second PMIC.

8. The method of claim 7 , wherein the time-critical alert signal is transmitted through a back power protection (BPP) rail.

9. The method of claim 7 , wherein the baseband processor (BP) includes a back power protection (BPP) alert block.

10. The method of claim 9 , wherein the BPP alert block is active only when the baseband processor (BP) is powered ON by the second PMIC.

11. The method of claim 10 wherein the BPP alert block is a pull down block to set the time-critical alert signal.

12. The method of claim 7 , wherein the time-critical alert signal is independent of a data bus communication protocol.

13. The method of claim 1 , wherein the first BPP supply output is carried on a first BPP rail and the second BPP supply output is carried on a second BPP rail, wherein the first BPP rail is a separate rail from the second BPP rail.

14. The method of claim 13 , wherein the first BPP rail includes a first automatic power back-feed prevention circuit and the second BPP rail includes a second automatic power back-feed prevention circuit.

15. The method of claim 14 , wherein the first automatic power back-feed prevention circuit includes a first diode, and the second automatic power back-feed prevention circuit each include a second diode.

16. The method of claim 1 , further comprising implementing the logical OR function by using one or more combinational logic elements that includes a AND gate, an OR gate, a NAND gate, a NOR gate, an XOR gate or an inverter gate.

17. A System on a Chip (SOC) with back power protection (BPP), the SOC comprising:
a first power management integrated circuit (PMIC);
an application processor (AP) coupled to the first PMIC, wherein the AP serves as a master processor;
a second power management integrated circuit (PMIC) different from the first PMIC;
a baseband processor (BP) coupled to the second PMIC, wherein the BP serves as a communications processor;
a logical OR function coupled to the baseband processor (BP);
a first back power protection (BPP) rail for carrying a first back power protection (BPP) supply output from the first PMIC; and
a second back power protection (BPP) rail for carrying a second back power protection (BPP) supply output from the second PMIC, wherein the second BPP rail is a separate rail from the first BPP rail.

18. The SOC of claim 17 , wherein the logical OR function generates a composite BPP power based on the first BPP supply output and the second BPP supply output.

19. The SOC of claim 18 , wherein the logical OR function inputs the composite BPP power to the baseband processor (BP).

20. The SOC of claim 19 , further comprising a back power protection (BPP) alert block.

21. The SOC of claim 20 , wherein the BPP alert block is a pull down block to set a time-critical alert signal.

22. The SOC of claim 21 , the BPP alert block is active only when the baseband processor (BP) is powered ON by the second PMIC.

23. The SOC of claim 21 , wherein the time-critical alert signal is independent of a data bus communication protocol.

24. The SOC of claim 17 , wherein the first BPP rail includes a first automatic power back-feed prevention circuit and the second BPP rail includes a second automatic power back-feed prevention circuit.

25. An apparatus for implementing back power protection (BPP) in a System on a Chip (SOC), the apparatus comprising:
means for transmitting a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function;
means for transmitting a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function;
means for generating a composite BPP power based on the first BPP supply output and the second BPP supply output, wherein the means for generating is the logical OR function; and
means for inputting the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.

26. The apparatus of claim 25 , further comprising means for generating a time-critical alert signal based on a back power protection (BPP) input signal to the baseband processor (BP).

27. The apparatus of claim 26 , wherein the back power protection (BPP) input signal is the composite BPP power.

28. The apparatus of claim 27 , further comprising means for transmitting the time-critical alert signal to at least one of the first PMIC and the second PMIC.

29. A non-transitory computer-readable medium storing computer executable code, operable on a device comprising at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement back power protection (BPP) in a System on a Chip (SOC), the computer executable code comprising:
instructions for causing a computer to transmit a first back power protection (BPP) supply output from a first power management integrated circuit (PMIC) to a logical OR function;
instructions for causing the computer to transmit a second back power protection (BPP) supply output from a second power management integrated circuit (PMIC) to the logical OR function;
instructions for causing the computer to use the logical OR function to generate a composite BPP power based on the first BPP supply output and the second BPP supply output; and
instructions for causing the computer to input the composite BPP power to a baseband processor (BP), wherein the baseband processor (BP) is coupled to the second PMIC.

30. The non-transitory computer-readable medium of claim 29 , further comprising instructions for causing the computer to generate a time-critical alert signal based on the composite BPP power and to transmit

Assignees

• Qualcomm Inc

Inventors

• Mishra Lalan Jee
• Wietfeldt Richard Dominic
• Tan Chiew-Guan
• Tu Alex Kuang-Hsuan

Classifications

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F1/263 Primary

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title