Multiple input multiple output regulator controller system

Patent metadata

Field	Value
Publication number	US-10627839-B2
Application number	US-201615250737-A
Country	US
Kind code	B2
Filing date	Aug 29, 2016
Priority date	Mar 2, 2016
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

Circuit techniques control multiple regulator circuits. Regulator circuits are configured to time share voltage control circuitry. The voltage control circuitry may include multiple sets of switches to selectively couple a voltage control circuit with a selected voltage regulation loop of one of the regulators.

First claim

What is claimed is:

1. A circuit comprising:
a plurality of regulator circuits each configured to receive a voltage control signal, and to output a regulated voltage signal, each regulator circuit comprising a capacitor coupled with the voltage control node to store a control voltage;
a voltage control circuit having an output selectively coupled with the voltage control nodes of the plurality of regulator circuits, the voltage control circuit having an input configured to sense regulated voltage signals output from the plurality of regulator circuits and to output the voltage control signal to set the control voltages of the plurality of regulator circuits;
at least one buffer circuit having a buffer circuit input and a buffer circuit output;
a first set of switches configured to selectively couple the output of the voltage control circuit with a selected one of the voltage control nodes of the plurality of regulator circuits via the at least one buffer circuit to precharge a compensation capacitor coupled to the output of the voltage control circuit with the stored control voltage of the selected voltage control node before the voltage control signal is coupled to the selected one of the voltage control nodes; and
a second set of switches configured to selectively couple a selected one of the regulated voltage signals output from the plurality of regulator circuits with the input of the voltage control circuit.

2. The circuit of claim 1 , wherein the at least one buffer circuit is one of a plurality of buffer circuits; and
wherein the buffer circuit input of the at least one buffer circuit is coupled with at least one voltage control node of the plurality of regulator circuits and the buffer circuit output of the at least one buffer circuit is coupled with the voltage control circuit to precharge the compensation capacitor coupled to the output of the voltage control circuit.

3. The circuit of claim 2 , further comprising a third set of switches configured to selectively couple the voltage control nodes of the plurality of regulator circuits with the output of the voltage control circuit through the plurality of buffer circuits to precharge the compensation capacitor coupled to the output of the voltage control circuit.

4. The circuit of claim 2 , further comprising a third set of switches configured to selectively couple the voltage control nodes of the plurality of regulator circuits with the buffer input of the at least one buffer circuit, the buffer output of the at least one buffer circuit coupled to the output of the voltage control circuit.

5. The circuit of claim 2 , wherein the at least one buffer circuit is coupled with the output of the voltage control circuit during a first time interval, the selected one of the voltage control nodes of the plurality of regulator circuits is coupled with the output of the voltage control circuit through one of the first set of switches during a second time interval following the first time interval, and the selected one of the regulated voltage signals output from the plurality of regulator circuits is coupled with the input of the voltage control circuit through one of the second set of switches during a third time interval overlapping the first time interval and the second time interval.

6. The circuit of claim 1 , wherein the at least one buffer circuit is configured to provide routing separation between the voltage control circuit and the regulator circuit.

7. The circuit of claim 6 , wherein the at least one buffer circuit comprises a current regulation loop coupled between a second terminal of a transistor and a first terminal of the transistor, the current regulation loop including a plurality of mirror transistors.

8. The circuit of claim 1 , wherein each regulator circuit further comprises a buffer circuit having a buffer circuit input coupled to the voltage control node to receive the control voltage and a buffer circuit output configured in a voltage control loop to set the regulated voltage signal at the output of the regulator.

9. The circuit of claim 1 , further comprising a plurality of clock intervals, the first set of switches selectively coupling the output of the voltage control circuit with the selected one of the voltage control nodes during a first clock interval, and the second set of switches selectively coupling the selected one of the regulated voltage signals output from the plurality of regulator circuits with the input of the voltage control circuit during at least a second clock interval, the second clock interval overlapping the first clock interval.

10. The circuit of claim 1 , wherein the voltage control circuit comprises a resistor divider circuit having an input coupled with the second plurality of switches to receive the selected one of the regulated voltage signals from the plurality of regulator circuits and an output configured to provide a feedback voltage signal.

11. The circuit of claim 10 , wherein the resistor divider circuit comprises a variable resistance element to adjust a resistance value based on the selected one of the regulated voltage signals output from the plurality of regulator circuits.

12. The circuit of claim 10 , wherein the voltage control circuit further comprises an amplifier including:
a first input coupled with the resistor divider circuit to receive the feedback voltage signal;
a second input coupled to receive a reference voltage signal; and
an output to generate the voltage control signal based on comparing the feedback voltage signal with the reference voltage signal.

13. The circuit of claim 1 , wherein a first regulated voltage signal output from a first one of the plurality of regulator circuits is different than a second regulated voltage signal output from a second one of the plurality of regulator circuits.

14. The circuit of claim 1 , wherein the voltage control circuit, the first set of switches and the second set of switches form a voltage regulation loop for each of the plurality of regulators, the voltage regulation loop configured to regulate the control voltage of the voltage control nodes of the plurality of regulator circuits.

15. The circuit of claim 14 , wherein the voltage regulation loop forms a discrete-time voltage regulation loop for each of the plurality of regulator circuits at different time intervals.

16. The circuit of claim 1 , wherein one or more regulator circuits further comprise a current control circuit.

17. The circuit of claim 16 , wherein the current control circuit forms continuous-time current regulation loops for each regulator and wherein the current control circuit has a faster response time than a response time of the voltage control circuit.

18. The circuit of claim 16 , the current control circuit comprising:
a pass transistor having a first terminal to receive an input voltage for a selected regulator circuit, a second terminal to provide a regulated output voltage to an output node of the selected regulator circuit, and a control terminal;
a current sensing transistor having a first terminal coupled with the second terminal of the pass transistor at the output of the regulator circuit, a second terminal to output a loop current complementary to a load current at the output node of the selected regulator circuit, and a control terminal to receive the voltage control signal from the voltage control circuit; and
a current regulation loop coupled between the second terminal of the current sensing transistor and the control terminal of the pass transistor, the current regulation loop comprising a plurali

Assignees

• Qualcomm Inc

Inventors

• Ho Ngai Yeung
• Guan Hua

Classifications

• G05F1/46

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• G05F1/577

  for plural loads · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title