Method for testing an electronic device and an interface circuit therefore

Patent metadata

Field	Value
Publication number	US-10627445-B2
Application number	US-201816043196-A
Country	US
Kind code	B2
Filing date	Jul 24, 2018
Priority date	Jul 24, 2017
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A method and interface circuit for testing an electronic device with a single logic pin is disclosed. The comprises forming a data stream having three level bands; inputting the data stream through a single logic pin; and decoding the data stream to identify a scan_in signal, a scan_shift_enable signal and a scan_out signal and returning contemporaneously a scan_out signal as an output through the same logic pin. The interface circuit includes a decoder connected to the single logic pin.

First claim

What is claimed is:

1. A method for testing an electronic device, said method comprising:
forming an input data stream having three level bands;
inputting the input data stream through a logic pin; and
decoding the input data stream to identify a scan_in signal, a scan_shift_enable signal and a scan_clock signal; and returning contemporaneously a scan_out signal as an output through the same logic pin.

2. The method of claim 1 , wherein the three level bands are one of three voltage bands or three current bands.

3. The method of claim 1 , wherein one of the three level bands is weakly driven and the other two of the three level bands are strongly driven.

4. The method of claim 1 , wherein the decoding of the data stream comprises comparing data values in the input data stream with comparator threshold levels for detecting actual level within the three level bands.

5. The method of claim 4 , wherein the data values in the data steam are on input offset by returned scan_out levels on the output.

6. The method of claim 1 , wherein a transition between one of the three level bands to another one of the three level bands defines a clock cycle edge.

7. The method of claim 1 , wherein the input data stream further comprises a plurality of test values.

8. The method of claim 7 , wherein the test values are shifted and captured into a scan shift register after detection of a scan_shift_enable signal.

9. An interface circuit for applying a data stream for a testing an electronic device through a single logic input pin connected to the electronic device comprising:
a level detection circuit connected to the single logic input pin, the level detection circuit being configured to detect one of three level bands in the data stream;
a decoder connected to the level detection circuit for generating a group of signals comprising a scan_in signal, a scan_shift_enable signal and a scan_clock signal, applying the generated group of signals to a shift scan register, and adapted to shift contemporaneously out the values captured in the scan shift register back out the same logic pin.

10. The interface circuit of claim 9 , being configured to generate a clock signal from the data stream.

11. An electronic device comprising a shift scan register and an interface circuit for applying a data stream for a testing an electronic device through a single logic input pin connected to the electronic device comprising:
a level detection circuit connected to the single logic input pin, the level detection circuit being configured to detect one of three level bands in the data stream;
a decoder connected to the level detection circuit for generating a group of signals comprising a scan_in signal, a scan_shift_enable signal and a scan_clock signal, applying the generated group of signals to a shift scan register, and adapted to shift contemporaneously out the values captured in the scan shift register back out the same logic pin.

12. An electronic device comprising a shift scan register and an interface circuit for applying a data stream for a testing an electronic device through a single logic input pin connected to the electronic device comprising:
a level detection circuit connected to the single logic input pin, the level detection circuit being configured to detect one of three level bands in the data stream;

a decoder connected to the level detection circuit for generating a group of signals comprising a scan_in signal, a scan_shift_enable signal and a scan_clock signal, applying the generated group of signals to a shift scan register, and adapted to shift contemporaneously out the values captured in the scan shift register back out the same logic pin, wherein the interface circuit being configured to generate a clock signal from the data stream.

Assignees

• Tdk Micronas Gmbh
• TDK—Micronas GmbH

Inventors

• Bradford Jonathan

Classifications

• G01R31/31712 Primary

  Input or output aspects · CPC title

• H04L25/4923

  using ternary codes (H04L25/4927 takes precedence) · CPC title

• G01R31/31713

  Input or output interfaces for test, e.g. test pins, buffers (for scan test G01R31/318572) · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318533 Primary

  using scanning techniques, e.g. LSSD, Boundary Scan, JTAG · CPC title