Demodulator circuit and method for demodulation

Patent metadata

Field	Value
Publication number	US-10623218-B2
Application number	US-201615580843-A
Country	US
Kind code	B2
Filing date	Jun 9, 2016
Priority date	Jun 15, 2015
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A demodulator circuit receives an envelope signal for comparison against a switched reference signal that is generated as a function of the envelope signal and as a function of an output signal of the demodulator circuit. The switched reference signal is filtered by an RC filter prior to comparison. The output signal is dependent on a difference between the filtered switched reference signal and the envelope signal.

First claim

The invention claimed is:

1. A demodulator circuit, comprising:
an input configured to receive an envelope signal,
a reference generator configured to generate a switched reference signal as a function of the envelope signal and as a function of an output signal of the demodulator circuit,
a filter circuit configured to filter the switched reference signal and generate a filtered switched reference signal, and
a comparator having a first input configured to receive the envelope signal and a second input configured to receive the filtered output signal, said comparator operable to output a demodulated output signal as a function of a difference between the envelope signal and the filtered switched reference signal,
wherein the reference generator comprises:
an up-converter circuit configured to provide an increased signal in response to the envelope signal;
a first switch actuated in response to the output signal to provide the increased signal to change the switched reference signal;
a down-converter circuit configured to provide a decreased signal in response to the envelope signal; and
a second switch actuated in response to an inversion of the output signal to provide the decreased signal to change the switched reference signal.

2. The demodulator circuit according to claim 1 , wherein:
the up-converter circuit comprises a circuit configured to amplify the envelope signal to generate the increased signal; and
the down-converter circuit comprises a circuit configured to attenuate the envelope signal to generate the decreased signal.

3. The demodulator circuit according to claim 2 ,
wherein the circuit of the up-converter circuit is an amplifier with an adjustable amplification ratio, and
wherein the circuit of the down-converter circuit is an attenuator with an adjustable attenuation ratio.

4. The demodulator circuit according to claim 1 ,
wherein a level of the increased signal is higher than a level of the envelope signal by a first adjustable ratio, and
wherein a level of the decreased signal is lower than the level of the envelope signal by a second adjustable ratio.

5. The demodulator circuit according to claim 1 , wherein the envelope signal is a rectified Amplitude Shift Keying (ASK) modulated signal.

6. The demodulator circuit according to claim 1 , wherein the output signal is a digital baseband signal.

7. The demodulator circuit according to claim 1 , wherein the filter circuit comprises a low-pass filter having a variable resistor and a capacitor, and wherein a connection node between the variable resistor and the capacitor provides the filtered switched reference signal.

8. The demodulator circuit according to claim 1 , wherein the comparator has a built-in hysteresis.

9. A demodulator circuit, comprising:
an input configured to receive an envelope signal,
a reference generator configured to generate a switched reference signal as a function of the envelope signal and as a function of an output signal of the demodulator circuit,
a filter circuit configured to filter the switched reference signal and generate a filtered switched reference signal, and
a comparator having a first input configured to receive the envelope signal and a second input configured to receive the filtered output signal, said comparator operable to output a demodulated output signal as a function of a difference between the envelope signal and the filtered switched reference signal;
wherein the reference generator comprises:
a resistive divider having a first tap node outputting an increased signal in response to the envelope signal and a second tap node outputting a decreased signal in response to the envelope signal;
a first switch actuated in response to the output signal to provide the increased signal to change the switched reference signal; and
a second switch actuated in response to an inversion of the output signal to provide the decreased signal to change the switched reference signal.

10. The demodulator circuit according to claim 9 , wherein the resistive divider comprises:
a first resistor coupled between the first tap node and a third tap node coupled to the first input of the comparator;
a second resistor coupled between the third tap node and the second tap node; and
a third resistor coupled between the second tap node and a reference node.

11. The demodulator circuit according to claim 10 , wherein at least one of the first, second and third resistors is a variable resistor.

12. The demodulator circuit according to claim 9 ,
wherein a level of the increased signal is higher than a level of the envelope signal by a first adjustable ratio, and
wherein a level of the decreased signal is lower than the level of the envelope signal by a second adjustable ratio.

13. The demodulator circuit according to claim 9 , wherein the envelope signal is a rectified Amplitude Shift Keying (ASK) modulated signal.

14. The demodulator circuit according to claim 9 , wherein the output signal is a digital baseband signal.

15. The demodulator circuit according to claim 9 , wherein the filter circuit comprises a low-pass filter having a variable resistor and a capacitor, and wherein a connection node between the variable resistor and the capacitor provides the filtered switched reference signal.

16. The demodulator circuit according to claim 9 , wherein the comparator has a built-in hysteresis.

17. A method for demodulation, comprising:
generating a switched reference signal as a function of an envelope signal and as a function of a demodulator output signal, wherein generating comprises:
producing an increased signal by up-converting the envelope signal;
producing a decreased signal by down-converting the envelope signal;
switching to select the increased signal as the switched reference signal in response to a first logic state of the demodulator output signal; and
switching to select the decreased signal as the switched reference signal in response to a second logic state, opposite the first logic state, of the demodulator output signal;

filtering the switched reference signal to provide a filtered switched reference signal; and
comparing the filtered switched reference signal with the envelope signal to output the demodulator output signal.

18. The method of claim 17 ,
wherein up-converting the envelope signal comprises increasing a level of the envelope signal to provide the increased signal; and
wherein down-converting the envelope signal comprises decreasing a level of the envelope signal to provide the decreased signal.

19. The method of claim 18 ,
wherein increasing the level comprises amplifying the envelope signal; and
wherein decreasing the level comprises attenuating the envelope signal.

20. The method of claim 17 , wherein the envelope signal is a rectified Amplitude Shift Keying (ASK) modulated signal.

21. The method of claim 17 , wherein the output signal is a digital baseband signal.

22. A method for demodulation, comprising:
generating a switched reference signal as a function of an envelope signal and as a function of a demodulator output signal, wherein generating comprises:
producing an increased signal from the envelope signal;
producing a decreased signal from the envelope signal;
changing the switched reference signal using the increased signal in response to the demodulator output signal; and
changing the switched reference signal using the decreased signal in response to an inversion of the demodulator outp

Assignees

• St Microelectronics Int Nv

Inventors

• Kunc Vinko
• Pevec Albin
• Kovacic Kosta

Classifications

• H03D1/22

  Homodyne or synchrodyne circuits {(receiver circuits H04B1/30)} · CPC title

• H04L27/261

  Details of reference signals · CPC title

• H03D1/18

  of semiconductor devices · CPC title

• H04L27/06 Primary

  Demodulator circuits; Receiver circuits · CPC title

• H03D1/02

  Details · CPC title