System and method of calibrating input signal to successive approximation register (SAR) analog-to-digital converter (ADC) in ADC-assisted time-to- digital converter (TDC)

Patent metadata

Field	Value
Publication number	US-10623010-B2
Application number	US-201816017564-A
Country	US
Kind code	B2
Filing date	Jun 25, 2018
Priority date	Sep 9, 2016
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

An apparatus and a method are provided. The apparatus includes an analog-to-digital converter (ADC) driver; and an ADC that is electrically coupled to the ADC driver. The method includes setting, by an analog-to-digital converter (ADC) driver, a desired common-mode control value based on the held voltage; and setting, by the ADC driver, a desired gain control value based on the held voltage.

First claim

What is claimed is:

1. An apparatus, comprising:
a counter array, where the counter array counts a number of cycles;
an analog-to-digital converter (ADC) driver that is electrically coupled to the counter array; and
an ADC that is electrically coupled to the ADC driver.

2. The apparatus of claim 1 , wherein the ADC driver includes one or more of a common-mode control value and a gain control value.

3. The apparatus of claim 1 , wherein the ADC adjusts a common-mode control value until the ADC completes an analog-to-digital conversion.

4. The apparatus of claim 1 , wherein the ADC adjusts a gain control value until ADC data from the ADC is not clipped.

5. The apparatus of claim 1 , further comprising a plurality of time-to-digital-converter (TDC) buffers, an ADC driver calibrator connected to the ADC driver and the counter array.

6. The apparatus of claim 5 , further comprising an interpolating resistive network connected to outputs of the plurality of TDC buffers.

7. The apparatus of claim 5 , further comprising a multiplexer connected to the outputs of the plurality of TDC buffers.

8. The apparatus of claim 7 , wherein the ADC driver is comprised of a programmable ADC driver connected to an output of the multiplexer.

9. The apparatus of claim 1 , further comprising a plurality of time-to-digital converter (TDC) buffers that each comprise:
an n-channel metal oxide semiconductor field effect transistor (NMOSFET);
a first current source;
a p-channel metal oxide semiconductor field effect transistor (PMOSFET); and
a second current source.

10. The apparatus of claim 5 , wherein each of the plurality of TDC buffers is one of a unity-gain buffer or a programmable-gain buffer.

11. A method, comprising:
counting, by a counter array, a number of cycles;
setting, by an analog-to-digital converter (ADC) driver electrically coupled to the counter array, a desired common-mode control value based on the held voltage; and
setting, by the ADC driver, a desired gain control value based on the held voltage.

12. The method of claim 11 , further comprising receiving, by a phase/frequency detector (PDF) a reference clock signal, a feedback clock signal, and outputting an enable signal.

13. The method of claim 11 , wherein counting, by the counter array, a number of cycles comprises counting, by the counter array, a number of cycles in a ring oscillator having a plurality of stages; and
further comprising suspending a ring oscillator after a desired number of cycles in the ring oscillator to hold a voltage at an output of the ring oscillator.

14. The method of claim 13 , wherein the ring oscillator includes a plurality of buffers connected in a ring, and wherein each of the outputs of the ring oscillator are connected to one of the plurality of buffers, respectively.

15. The method of claim 13 , further comprising buffering the outputs of the ring oscillator by a plurality of buffers each comprising:
an n-channel metal oxide semiconductor field effect transistor (NMOSFET);
a first current source;
a p-channel metal oxide semiconductor field effect transistor (PMOSFET); and
a second current source.

16. The method of claim 11 , further comprising adjusting the gain control value until ADC data is not clipped.

17. The method of claim 11 , further comprising linearizing a fractional portion of the cycles of a ring oscillator by an interpolating resistive network.

18. The method of claim 17 , further comprising converting the linearized fractional portion of the cycles of the ring oscillator to a voltage for fine time-to-digital conversion.

19. The method of claim 15 , further comprising, multiplexing the buffered outputs of the ring oscillator by a multiplexer.

20. The method of claim 11 , further comprising programming the ADC driver.

Assignees

• Samsung Electronics Co Ltd

Inventors

• LOKE Wing-Fai
• Yao Chih-Wei

Classifications

• H03M1/183

  the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter · CPC title

• G04F10/04 Primary

  by counting pulses or half-cycles of an AC {(G04F10/005 takes precedence)} · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title

• H03L7/0996

  Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator · CPC title

• H03L7/0998

  using phase interpolation · CPC title