Method and system of a resonant power converter

Patent metadata

Field	Value
Publication number	US-10622883-B2
Application number	US-201816010578-A
Country	US
Kind code	B2
Filing date	Jun 18, 2018
Priority date	Jun 18, 2018
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

Resonant power converters. Example embodiments are integrated circuit controllers for a resonant power converter, the controllers including: a frequency controller configured to control frequency of signals driven to a high-side gate terminal and a low-side gate terminal; a fault detector configured to sense an overcurrent condition of a primary winding of the resonant power converter, and to assert an overcurrent signal responsive to the overcurrent condition; a feedback controller that, during periods of time when the overcurrent signal is de-asserted, is configured to sense a signal representative of output voltage by way of the feedback terminal and to create an intermediate signal; and the feedback controller further configured to, during periods when the overcurrent signal is asserted, modify the intermediate signal to increase the frequency of the signals driven to the high-side gate terminal and the low-side gate terminal.

First claim

What is claimed is:

1. A method of operating a power converter comprising:
sensing a signal representative of an output voltage provided to a load;
creating an intermediate signal using the signal representative of the output voltage;
sensing a signal representative of a current in a primary winding of a transformer;
controlling frequency of an alternating current (AC) signal applied to the primary winding by way of a high-side field effect transistor (FET) and a low-side FET, the high-side FET selectively couples an input voltage to the primary winding, and the low-side FET selectively couples the primary winding to ground;
asserting a fault input to a fault counter each time the signal representative of the current in the primary winding exceeds a predetermined threshold;
asserting, by the fault counter, an overcurrent output responsive to a first predetermined number of assertions of the fault input within a second predetermined number of cycles of the frequency of the AC signal;
during periods of time when the overcurrent output is de-asserted, controlling turn off of the high-side FET in each cycle of the AC signal based on the intermediate signal and the signal representative of the current in the primary winding; and
during periods of time when the overcurrent output is asserted, increasing the frequency of the AC signal by modifying the intermediate signal to create a modified signal, and by controlling turn off of the high-side FET in each cycle based on the modified signal and the signal representative of the current in the primary winding.

2. The method of claim 1 :
wherein creating the intermediate signal further comprises applying a gain to the signal representative of the output voltage; and
wherein modifying further comprises changing the gain used to create the intermediate signal, the modification from an original gain to a modified gain different than the original gain.

3. The method of claim 2 further comprising, after the changing the gain, returning to the original gain a predetermined amount of time after the changing.

4. The method of claim 3 wherein the predetermined amount of time is at least one selected from a group comprising: a predetermined number of cycles of the AC signal applied to the primary winding; and a predefined duration of a timer.

5. The method of claim 1 :
wherein creating the intermediate signal further comprises applying a bias to the signal representative of the output voltage; and
wherein modifying further comprises changing the bias used to create the intermediate signal.

6. The method of claim 5 wherein changing the bias further comprises reducing the bias.

7. The method of claim 1 :
wherein creating the intermediate signal further comprises applying a gain and a bias to the signal representative of the output voltage; and
wherein modifying the intermediate signal further comprises changing at least one selected from a group consisting of: the gain; and the bias.

8. The method of claim 1 :
wherein controlling frequency further comprises controlling based on sensing the signal representative of the current in the primary winding through a current-sense terminal of a primary-side controller.

9. The method of claim 1 further comprising:
de-asserting the overcurrent output after a third predetermined number of cycles the frequency of the AC signal in which the fault input is not asserted; and then
returning to an original intermediate signal.

10. The method of claim 1 further comprising:
asserting, by the fault counter, a fault output responsive to third predetermined number of assertions of the fault input within a fourth predetermined number of cycles of the frequency of the AC signal; and
ceasing operation of the power converter responsive to assertion of the fault output.

11. The method of claim 10 wherein asserting the fault output further comprises asserting the fault output responsive to between and including 5 and 10 assertions of the fault input in a contiguous set of more than 30 cycles of the frequency of the AC signal.

12. The method of claim 1 wherein sensing a signal representative of output voltage further comprises:
applying the output voltage to a diode of an optocoupler;
creating the signal representative of the output voltage by a transistor of the optocoupler.

13. An integrated circuit comprising:
a driver circuit within the integrated circuit;
a frequency controller within the integrated circuit and coupled to the driver circuit, the frequency controller configured to control frequency of signals driven to a high-side gate terminal and a low-side gate terminal;
a first comparator within the integrated circuit, the first comparator defining a first input coupled to a current sense terminal, a second input coupled to a reference voltage, and a comparator output, the first comparator configured to assert the comparator output each time a signal on the current sense terminal transitions through the reference voltage;
a fault counter within the integrated circuit, the fault counter defining a fault input coupled to the comparator output, and an overcurrent output, the fault counter configured to assert the overcurrent output responsive to a first predetermined number of assertions of the fault input within a second predetermined number of cycles of the frequency of the signals driven to the high-side gate terminal and low side gate terminal;
a feedback controller within the integrated circuit, the feedback controller comprising:
a ramp compensation circuit defining an intermediate output, an overcurrent input coupled to the overcurrent output, and a feedback input coupled to a feedback terminal;
a second comparator defining a first input coupled to the current sense terminal, a second input coupled to the intermediate output, and a comparator output coupled to the frequency controller;
during periods of time when the overcurrent input is de-asserted, the ramp compensation circuit configured to sense a signal representative of an output voltage by way of the feedback terminal and to create an intermediate signal applied to the intermediate output; and
during periods when the overcurrent input is asserted, the ramp compensation circuit configured to modify the intermediate signal to increase the frequency of the signals driven to the high-side gate terminal and the low-side gate terminal.

14. The integrated circuit of claim 13 further comprising:
the ramp compensation circuit, during periods of time when the overcurrent input is de-asserted, is configured to apply a gain to the signal representative of the output voltage to create the intermediate signal; and
the ramp compensation circuit, during periods of time when the overcurrent input is asserted, is further configured to change the gain used to create the intermediate signal from an original gain to a modified gain different than the original gain.

15. The integrated circuit of claim 14 wherein the ramp compensation circuit is further configured return to the original gain responsive to de-assertion the overcurrent input.

16. The integrated circuit of claim 13 further comprising:
the ramp compensation circuit, during periods of time when the overcurrent input is de-asserted, is configured to apply a bias to the signal representative of the output voltage to create the intermediate signal; and
the ramp compensation circuit, during periods of time when the overcurrent input is asserted, is configured to change the bias from an original bias to a modified bias different than the original bias.

17. The integra

Assignees

• Semiconductor Components Ind Llc

Inventors

• Drda Vaclav
• Stuler Roman

Classifications

• H02M1/32 Primary

  Means for protecting converters other than automatic disconnection · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M3/33569

  having several active switching elements (H02M3/3353 takes precedence) · CPC title

• H02M2001/0009

  Electricity · mapped topic

• H02M2001/0025

  Electricity · mapped topic