Method of manufacturing semiconductor device using multiple patterning techniques

Patent metadata

Field	Value
Publication number	US-10622256-B2
Application number	US-201615083248-A
Country	US
Kind code	B2
Filing date	Mar 28, 2016
Priority date	Apr 15, 2015
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a first sacrificial layer on a substrate including a first region and a second region;
forming a first pattern on the first sacrificial layer in the first region and a first mark generation layer on the first sacrificial layer in the second region;
forming a first key pattern on the first mark generation layer;
forming a first mark generation pattern by partially etching the first mark generation layer using the first key pattern as an etch mask;
forming a second pattern by etching the first sacrificial layer in the first region using the first pattern as an etch mask;
forming a second key pattern by etching the first sacrificial layer in the second region using the first mark generation pattern as an etch mask;
forming first spacers on sidewalls of the second pattern and first key spacers on sidewalls of the second key pattern;
forming first fin-shaped patterns in the first region by partially etching the substrate using the first spacers as etch masks; and
forming a trench key in the second region.

2. The method of claim 1 , further comprising forming a second mark generation layer between the substrate and the first sacrificial layer in the second region,
wherein the second key pattern is formed on the second mark generation layer and overlaps with the second mark generation layer.

3. The method of claim 2 , further comprising:
forming a second mark generation pattern by etching the second mark generation layer using the second key pattern and the first key spacers as etch masks;
removing the second key pattern; and
forming the trench key by partially etching the substrate using the second mark generation pattern as an etch mask.

4. The method of claim 3 , further comprising:
forming a mask layer between the substrate and the second mark generation layer,
wherein the mask layer includes a lower mask layer and an upper mask layer sequentially stacked on the substrate, and
the second mark generation layer includes a material that has a high etch selectivity with respect to the upper mask layer.

5. The method of claim 4 , further comprising:
etching the mask layer using the second mark generation pattern as an etch mask to form a mask pattern.

6. The method of claim 5 , further comprising:
etching the substrate using the mask pattern as an etch mask to form the trench key.

7. The method of claim 1 , further comprising:
forming a blocking pattern covering the first pattern in the first region,
wherein the step of forming the blocking pattern is performed by the same photolithography process forming the first key pattern.

8. The method of claim 7 , further comprising:
forming a second sacrificial layer covering the first pattern and the first mark generation layer on the first sacrificial layer; and
patterning the second sacrificial layer to form the first key pattern and the blocking pattern.

9. The method of claim 1 , further comprising:
forming second key spacers on sidewalls of the first key pattern; and
forming a recess in the first mark generation layer by partially etching the first mark generation layer using the first key pattern and the second key spacers as etch masks to form the first mark generation pattern.

10. The method of claim 9 , further comprising:
after removing the first key pattern, etching the first sacrificial layer using the second key spacers and the first mark generation pattern as etch masks to form the second key pattern.

11. The method of claim 1 , wherein the substrate further includes a third region, and the method further comprises forming a third pattern on the first sacrificial layer in the third region with the same process forming the first key pattern.

12. The method of claim 11 , further comprising:
forming second spacers on sidewalls of the third pattern;
forming a fourth pattern by etching the first sacrificial layer using the second spacers as etch masks;
forming third spacers on sidewalls of the fourth pattern; and
forming second fin-shaped patterns in the third region, by partially etching the substrate using the third spacers as etch masks.

13. The method of claim 12 , wherein a first pitch of the first fin-shaped patterns is formed to be greater than a second pitch of the second fin-shaped patterns.

14. The method of claim 1 , wherein the first mark generation layer is not formed in the first region.

15. A method of manufacturing a semiconductor device, the method comprising:
sequentially forming a mask layer, a first mark generation layer, and a first sacrificial layer on a substrate including a first region, a second region, and a third region, the first mark generation layer being formed between the mask layer and the first sacrificial layer in the third region;
forming a first pattern on the first sacrificial layer in the second region and a second mark generation layer on the first sacrificial layer of the third region;
forming a second pattern on the first sacrificial layer in the first region, a blocking pattern covering the first pattern, and a first key pattern on the second mark generation layer;
forming first spacers on sidewalls of the second pattern and first key spacers on sidewalls of the first key pattern;
forming a second mark generation pattern by partially etching the second mark generation layer using the first key pattern and the first key spacers as etch masks;
after forming the second mark generation pattern, removing the second pattern, the blocking pattern, and the first key pattern;
forming a third pattern in the first region by etching the first sacrificial layer using the first spacers as etch masks;
forming a fourth pattern in the second region by etching the first sacrificial layer using the first pattern as an etch mask;
forming a second key pattern on the first mark generation layer by etching the first sacrificial layer using the second mark generation pattern as an etch mask;
forming second spacers on sidewalls of the third pattern, third spacers on sidewalls of the fourth pattern, and second key spacers of sidewalls of the second key pattern; and
forming a first mark generation pattern exposing a top surface of the mask layer by etching the first mark generation layer using the second key pattern and the second key spacers as etch masks.

16. The method of claim 15 , further comprising:
removing the second key pattern, the third pattern, and the fourth pattern; and
forming first fin-shaped patterns in the first region, second fin-shaped patterns in the second region, and a trench key in the third region using the second spacers, the third spacers, and the first mark generation pattern, respectively.

17. A method of manufacturing a semiconductor device having a first region and a second region, the method comprising:
providing a substrate including in the first region and in the second region;
forming a first sacrificial layer on the substrate in the first region and in the second region;
forming a first pattern on the first sacrificial layer in the second region;
forming a first layer on the substrate in the first region and the second region, the first layer covering the first pattern;
after forming the first pattern, patterning the first layer to form be a patterned first layer, the patterned first layer including a second pattern on the first sacrificial layer in the first region,
wherein the first pattern in the second region is covered with the patterned first layer after the second pattern is formed;
forming in th

Assignees

• Mun Seung Jin
• Khang Dong Hoon
• Kim Woo Ram
• Kim Cheol
• Lee Dong Seok
• Choi Yong Joon
• Ha Seung Mo
• Kim Do Hyoung
• Samsung Electronics Co Ltd

Inventors

• Mun Seung-Jin
• KHANG Dong-Hoon
• KIM Woo-Ram
• Kim Cheol
• Lee Dong-Seok
• Choi Yong-Joon
• Ha Seung-Mo
• Kim Do-Hyoung

Classifications

• H01L21/823431 Primary

  Electricity · mapped topic

• H01L2223/54453

  Electricity · mapped topic

• H01L23/544

  Electricity · mapped topic

• H01L2223/54426

  Electricity · mapped topic

• H01L21/3086

  Electricity · mapped topic