Memory stripe with selectable size

Patent metadata

Field	Value
Publication number	US-10620983-B2
Application number	US-201615346178-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Nov 8, 2016
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A method of operating a virtual memory manager (VMM) in a computing system is provided. The method includes receiving a boot-up instruction, determining an amount of available configurable memory, determining a system logical memory block (LMB) size and selecting a memory stripe size for memory stripes respectively associated with LMBs provided within the available configurable memory. The selecting of the memory stripe size for the memory stripes is based in part on the determined amounts of the available configurable memory and the system LMB size.

First claim

What is claimed is:

1. A method of operating a virtual memory manager (VMM) in a computing system, the method comprising:
receiving a boot-up instruction;
determining an amount of available configurable memory (CM);
determining a system logical memory block (LMB) size; and
selecting a memory stripe size for memory stripes respectively associated with LMBs provided within the available CM based in part on the determined amounts of the available CM and the system LMB size,
wherein the selecting comprises selecting one of:
a first memory stripe size in an event the determined amount of the available CM is up to a first number of terabits (TBs) and the system LMB size is a 1 st -5 th multiple of a predefined LMB size;
a second memory stripe size, which is larger than the first memory stripe size, in an event the determined amount of the available configurable memory is greater than the first number of TBs and less than a second number of TBs and the system LMB size is the 5 th multiple of the predefined LMB size; or
a third memory stripe size, which is larger than the second memory stripe size, in an event the determined amount of the available configurable memory is greater than the second number of TBs and the system LMB size is the 5 th multiple of the predefined LMB size.

2. The method according to claim 1 , wherein the selecting is responsive to a user input.

3. The method according to claim 1 , wherein the first memory stripe size is 16 MB, the second memory stripe size is 32 MB and the third memory stripe size is 64 MB.

4. A computer program product for deployment in a computing system comprising:
available configurable memory (CM); and
a virtual memory manager (VMM), which is operably coupled to the available CM and has executable instructions stored thereon, which, when executed, cause the VMM to manage a configuration of the available CM during boot-up processes by:
determining an amount of available CM,
determining a system logical memory block (LMB) size, and
selecting a memory stripe size for memory stripes respectively associated with LMBs provided within the available CM based in part on the determined amounts of the available CM and the system LMB size,
wherein the selecting comprises selecting one of:
a first memory stripe size in an event the determined amount of the available CM is up to a first number of terabits (TBs) and the system LMB size is a 1 st -5 th multiple of a predefined LMB size;
a second memory stripe size, which is larger than the first memory stripe size, in an event the determined amount of the available CM is greater than the first number of TBs and less than a second number of TBs and the system LMB size is the 5 th multiple of the predefined LMB size; or
a third memory stripe size, which is larger than the second memory stripe size, in an event the determined amount of the available CM is greater than the second number of TBs and the system LMB size is the 5 th multiple of the predefined LMB size.

5. The computer program product according to claim 4 , wherein the first memory stripe size is a legacy memory stripe size.

6. The computer program product according to claim 4 , wherein the first memory stripe size is 16 MB, the second memory stripe size is 32 MB and the third memory stripe size is 64 MB.

7. A computing system, comprising:
available configurable memory (CM); and
a virtual memory manager (VMM), which is operably coupled to the available CM and configured to manage a configuration of the available CM during boot-up processes by:
determining an amount of available CM,
determining a system logical memory block (LMB) size, and
selecting a memory stripe size for memory stripes respectively associated with LMBs provided within the available CM based in part on the determined amounts of the available CM and the system LMB size,
wherein the VMM executes the selecting by selecting one of:
a first memory stripe size in an event the determined amount of the available CM is up to a first number of terabits (TBs) and the system LMB size is a 1 st -5 th multiple of a predefined LMB size;
a second memory stripe size, which is larger than the first memory stripe size, in an event the determined amount of the available configurable memory is greater than the first number of TBs and less than a second number of TBs and the system LMB size is the 5 th multiple of the predefined LMB size; or
a third memory stripe size, which is larger than the second memory stripe size, in an event the determined amount of the available configurable memory is greater than the second number of TBs and the system LMB size is the 5 th multiple of the predefined LMB size.

8. The computing system according to claim 7 , wherein:
instructions for executing the management of the configuration of the available configurable memory are stored in VMM system initialization code, and
the amount of available configurable memory and the system LMB size are both constant.

9. The computing system according to claim 7 , wherein the first memory stripe size is a legacy memory stripe size.

10. The computing system according to claim 7 , wherein the first memory stripe size is 16 MB, the second memory stripe size is 32 MB and the third memory stripe size is 64 MB.

Assignees

• IBM

Inventors

• Jaloma Jaime A
• Rogers Mark D

Classifications

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F9/4403 Primary

  Processor initialisation · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F12/023

  Free address space management · CPC title