Fine-grained clock resolution using low and high frequency clock sources in a low-power system

Patent metadata

Field	Value
Publication number	US-10620661-B2
Application number	US-201816222858-A
Country	US
Kind code	B2
Filing date	Dec 17, 2018
Priority date	Dec 17, 2017
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

A periodic output generator has a first clock source coupled to a first counter and a second clock source with a frequency greater than the first clock source, the second clock source coupled to a second counter, the first clock source operating continuously, the second clock source enabled when the first clock source reaches a count C1. The second clock source generates an output when a count C2 is reached, and the counters are reset and the process repeats. In another example, a timestamp generator has a high speed clock and a real time clock operative on a low speed clock. The timestamp generator receives an external event, turns on the high speed clock generator and counts high speed clock cycles C until the arrival of the next time stamp, and computes an event timestamp as the next timestamp less c/f, less the startup time of the high speed clock.

First claim

We claim:

1. A periodic time signal generator comprising:
a first clock source having a frequency f1 and coupled to a first counter which is initially reset;
a second clock source having a frequency f2 which is greater than f1 when the second clock source is powered on, the second clock source also having a turn-on delay of Ts, the second clock source output coupled to a second counter which is initially reset;
the second clock source not enabled until the first clock source reaches a count C1, upon which time power is applied to the second clock source;
an output pulse generated for one or more second clock source cycles when the second clock source reaches a count C2, after which the second clock source is powered off and the first and second counters are reset;
whereby the periodic time signal generator has an output interval substantially equal to C1/f1+C2/f2 plus Ts.

2. The periodic time generator of claim 1 where the first counter is initialized on reset to said count C1, said first counter thereafter counting down to 0, at which time said second oscillator is powered on.

3. The periodic time generator of claim 1 where the second counter is initialized on power-up to said count C2, said second counter thereafter counting down to 0, at which time said output is asserted.

4. The periodic time generator of claim 1 where said second counter is powered on by a switch which is enabled when said first counter reaches said count C1.

5. The periodic time generator of claim 1 where said first oscillator is a crystal oscillator.

6. The periodic time generator of claim 1 where said second oscillator is either a ring oscillator or an RC oscillator.

7. The periodic time generator of claim 1 where said first oscillator is used to calibrate said second oscillator.

8. The periodic time generator of claim 1 where said first oscillator is used to determine said Ts of said second oscillator.

9. The periodic time generator of claim 1 where the ratio of f1/f2 is greater than 100.

10. A method for clock generation operative on:
a first clock source having a frequency f1;
a second clock source operative to be powered on or powered off, the second clock source having a frequency f2 which is greater than f1 when the second clock source is powered on, the second clock source also having a turn-on delay of Ts;
a first counter coupled to the first clock source and incrementing on each first clock source cycle;
a second counter coupled to the second clock source and incrementing on each second clock source cycle;
the method comprising the canonical sequence:
a first step of powering off the second clock source and resetting the second counter;
a second step of resetting the first clock counter;
upon the first clock counter reaching a count C1, powering on the second clock source;
asserting an output for one or more second clock source cycles when the second clock source reaches a count C2;
returning to the first step.

11. The method of claim 10 where the periodic time signal generator has an output interval substantially equal to C1/f1+C2/f2+Ts.

12. The method of claim 10 where the first counter is initialized on reset to said count C1, the first counter thereafter counting down to 0, at which time the second oscillator is powered on.

13. The method of claim 10 where the second counter is initialized on power-up to said count C2, the second counter thereafter counting down to 0, at which time the output is asserted.

14. The method of claim 10 where the second counter is powered on by a switch when the first counter reaches the count C1.

15. The method of claim 10 where the first oscillator is a crystal oscillator.

16. The method of claim 10 where the second oscillator is a ring oscillator or an RC oscillator.

17. The method of claim 10 where the Ts value is determined by measurement using the first oscillator.

18. The method of claim 10 where the ratio of f1/f2 is greater than 100.

Assignees

• Redpine Signals Inc

Inventors

• Murali Partha Sarathy
• Anakala Nagaraja Reddy

Classifications

• H03B5/32

  being a piezoelectric resonator (selection of piezoelectric material H10N30/00) · CPC title

• G06F1/14 Primary

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F1/06 Primary

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• H03B5/02

  Details · CPC title