Electro-optical device and electronic apparatus

Patent metadata

Field	Value
Publication number	US-10620494-B2
Application number	US-201816232771-A
Country	US
Kind code	B2
Filing date	Dec 26, 2018
Priority date	Dec 27, 2017
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

In an element substrate of an electro-optical device, a semiconductor layer of a transistor has an L shape bending to overlap with both a scanning line and a data line. A first light shielding layer overlaps with a lower layer side of the semiconductor layer. A first light shielding wall and a second light shielding wall are provided on both sides of a semiconductor layer portion between a channel region and a second source/drain region (drain region) of the semiconductor layer. The first light shielding wall and the second light shielding wall to which a constant potential is applied prevent the semiconductor layer portion from being electrically affected even when the first light shielding wall and the second light shielding wall come close to the semiconductor layer portion.

First claim

What is claimed is:

1. An electro-optical device comprising:
a first substrate;
a pixel electrode provided on one surface side of the first substrate;
a scanning line provided in a layer between the first substrate and the pixel electrode, the scanning line extending in a first direction;
a data line provided in a layer between the first substrate and the pixel electrode, the data line extending in a second direction intersecting the scanning line;
a transistor including a semiconductor layer extending in each of the first direction and the second direction;
a first light shielding layer provided in a layer between the first substrate and the transistor, the first light shielding layer overlapping in a plan view with the semiconductor layer;
a first conductive layer provided in a layer between the transistor and the pixel electrode, the first conductive layer being supplied with a constant potential; and
a first interlayer insulating film provided in a layer between the first light shielding layer and the first conductive layer, wherein

the first light shielding layer is electrically coupled to the first conductive layer via a first contact hole and a second contact hole provided in the first interlayer insulating film in a manner extending along the semiconductor layer,
at least a source/drain region in the semiconductor layer extends in a plan view between the first contact hole and the second contact hole,
a first light shielding wall formed of a light shielding conductive material is provided on an inner wall of the first contact hole,
a second light shielding wall formed of a light shielding conductive material is provided on an inner wall of the second contact hole, and
at least a semiconductor layer portion in the semiconductor layer overlaps with an end portion on a source/drain region side of a gate electrode of the transistor via a gate insulating layer, the semiconductor layer onion being located between the first light shielding wall and the second light shielding wall,
the electro-optical device further comprising:
a second light shielding layer overlapping in a plan view with the semiconductor layer in a layer between the first light shielding layer and the semiconductor layer,
a third contact hole penetrating through a second interlayer insulating film interposed between the second light shielding layer and the gate electrode on an opposite side of the semiconductor layer portion to the source/drain region in a region overlapping in a plan view with the scanning line, and
a third light shielding wall formed of a conductive material covering an inner wall of the third contact hole.

2. The electro-optical device according to claim 1 , wherein the source/drain region is electrically coupled to the pixel electrode.

3. The electro-optical device according to claim 1 , wherein
the source/drain region includes
a first region electrically coupled to the pixel electrode, and
a second region interposed between a channel region and the first region, the second region having impurity concentration lower than that of the first region, and
the second region is entirely located between the first light shielding wall and the second light shielding wall.

4. The electro-optical device according to claim 1 , wherein the first light shielding wall and the second light shielding wall extend in the first direction along the semiconductor layer.

5. The electro-optical device according to claim 1 , wherein
the first light shielding wall serves as a first plug for filling the first contact hole, and
the second light shielding wall serves as a second plug for filling the second contact hole.

6. The electro-optical device according to claim 1 , wherein the first conductive layer has a light shielding property, and overlaps in a plan view with the semiconductor layer portion.

7. The electro-optical device according to claim 1 , wherein the first light shielding layer extends in the first direction to overlap in a plan view with the scanning line.

8. The electro-optical device according to claim 1 , wherein
the gate electrode includes
a first electrode portion overlapping with the semiconductor layer, and
a second electrode portion overlapping in a plan view with the scanning line, the second electrode portion protruding from the first electrode portion toward an opposite side to the source/drain region, and
the third contact hole is provided at a position overlapping in a plan view with the second light shielding layer and the second electrode portion.

9. The electro-optical device according to claim 1 , wherein
the scanning line is provided in a layer between the gate electrode and the pixel electrode, and
the gate electrode is electrically coupled, on an opposite side of the semiconductor layer portion to the source/drain region, to the scanning line via a fourth contact hole penetrating through a third interlayer insulating film interposed between the gate electrode and the scanning line.

10. The electro-optical device according to claim 1 , including a second conductive layer provided in a layer between the first conductive layer and the pixel electrode, wherein
the second interlayer insulating film is provided with
a fifth contact hole penetrating through a fourth interlayer insulating film in the second interlayer insulating film to partially communicate with the first contact hole, the fourth interlayer insulating film being interposed between the first conductive layer and the second conductive layer, and
a sixth contact hole penetrating through the fourth interlayer insulating film to partially communicate with the second contact hole, and
the first light shielding wall is integrally provided from the fifth contact hole to the first contact hole, and
the second light shielding wall is integrally provided from the sixth contact hole to the second contact hole.

11. The electro-optical device according to claim 10 , wherein
the second conductive layer includes a first capacitance electrode,
between the first conductive layer and the pixel electrode is provided a second capacitance electrode overlapping in a plan view with the first capacitance electrode via a dielectric layer, and the second capacitance electrode is electrically coupled to the pixel electrode.

12. The electro-optical device according to claim 1 , including
a second substrate facing the first substrate;
a common electrode formed on a surface on a first substrate side of the second substrate; and
an electro-optical layer provided between the first substrate and the second substrate, wherein
the electric potential serves as a common electric potential applied to the common electrode.

13. An electronic apparatus comprising the electro-optical device according to claim 1 .

14. An electro-optical device comprising:
a first substrate;
a pixel electrode provided on one surface side of the first substrate;
a scanning line provided in a layer between the first substrate and the pixel electrode, the scanning line extending in a first direction;
a data line provided in a layer between the first substrate and the pixel electrode, the data line extending in a second direction intersecting the scanning line;
a transistor including a semiconductor layer extending in each of the first direction and the second direction;
a first light shielding layer provided in a layer between the first substrate and the transistor, the first light shielding layer overlapping in a plan view with the semiconductor layer;
a first conductive layer provided in a layer between the transistor and the pixel electrode, the first conductive lay

Assignees

• Seiko Epson Corp

Inventors

• Oikawa Hiroyuki
• Nimura Toru
• Fujikawa Shinsuke

Classifications

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/136209 Primary

  Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136213

  Storage capacitors associated with the pixel electrode · CPC title