Kinematic chip to chip bonding

Patent metadata

Field	Value
Publication number	US-10620377-B1
Application number	US-201615084164-A
Country	US
Kind code	B1
Filing date	Mar 29, 2016
Priority date	Apr 1, 2015
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

The various technologies presented herein relate to integrating an IC having at least one waveguide incorporated therein with a v-groove array IC such that an optical fiber located in a v-groove is aligned relative to a waveguide in the IC maximizing optical coupling between the fiber and the waveguide. The waveguide IC and the v-groove array IC are bonded in a stacked configuration. Alignment of the waveguide IC and the array IC in the stacked configuration enables advantage to be taken of lithographic accuracy of features formed with respect to the Z-direction. Further, kinematic pins and sockets are utilized to provision accuracy in the X- and Z-directions, wherein advantage is taken of the placement accuracy and fabrication tolerance(s) which can be utilized when forming the and sockets. Accordingly, automated alignment of the waveguide IC and the array IC is enabled, facilitating accurate alignment of the respective waveguides and fibers.

First claim

What is claimed is:

1. An integrated circuit (IC) configuration comprising:
a first chip comprising:
a pin, wherein the pin extends outward from a first surface of the first chip, the pin has a proximal end located on the first surface of the first chip, a distal end, and a length therebetween such that the distal end is positioned outward from the first surface of the first chip;
a waveguide located in a first sidewall of the first chip, wherein the first sidewall adjoins the first surface of the first chip, and a first end of the waveguide is located at an exterior surface of the first sidewall; and
a first conductive pad located on the first surface of the first chip, wherein the first conductive pad comprises a malleable material; and

a second chip comprising:
a substrate having an upper surface, the substrate further comprising:
a channel formed in the upper surface of the substrate and extends along a portion of the upper surface, the channel having a first end located at an edge of the upper surface formed by the upper surface and a second sidewall of the substrate and a second end located at a distance along which the channel extends over the upper surface of the substrate; and
a socket formed into the substrate, wherein the socket has an inverted pyramidal shape comprising at least three socket sidewalls, at least one sidewall of the socket converges from an opening at the upper surface to an apex in the substrate, wherein the first chip is positioned on top of the second chip such that the distal end of the pin is located within the socket, and the first end of the channel is located in accordance with the location of the first end of the waveguide, and wherein the malleable material is configured to deform during location of the first chip and the second chip to form an electrical path between the first chip and the second chip.

2. The IC configuration of claim 1 , further comprising an optical fiber located in the channel, wherein the optical fiber is axially aligned along the length of the channel and a first end of the optical fiber is proximate to the first end of the waveguide wherein light is transmitted between the waveguide and the optical fiber.

3. The IC configuration of claim 2 , further comprising a clamp portion, wherein the clamp portion is configured to apply a clamping force upon the optical fiber to maintain location of the optical fiber, wherein the first end of the optical fiber is proximate to the first end of the waveguide.

4. The IC configuration of claim 2 , further comprising an optical couplant located between the first end of the optical fiber and the first end of the waveguide, the optical couplant configured to provide optical coupling for light transmission between the optical fiber and the waveguide.

5. The IC configuration of claim 1 , further comprising a standoff located on the first surface of the first chip, wherein the standoff maintains a separation distance between the first surface of the first chip and the upper surface of the second chip.

6. The IC configuration of claim 1 , further comprising a second conductive pad located on the upper surface of the second chip, wherein the second conductive pad is configured to touch the first conductive pad, the second conductive pad comprises the malleable material, wherein the malleable material deforms during location of the first chip and the second chip to form an electrical path between the first substrate and the second substrate.

7. The IC configuration of claim 1 , wherein the at least one wall of the socket is angled such that as a force is applied to the first chip during location of the first chip with the second chip, the distal end of the pin slides into the socket.

8. The IC configuration of claim 1 , wherein the pin comprises at least one of an oxide, nitride, metal, ceramic, an epoxy resin, a hardened epoxy resin, or benzocyclobutene (BCB).

9. The IC configuration of claim 1 , wherein the socket is formed by lithography.

10. An integrated circuit (IC) comprising:
a first die stacked on a second die, wherein the first die comprises a plurality of pins on a first surface of the first die, and the second die comprises a plurality of sockets on an upper surface of a substrate forming the second die, wherein a first socket in the plurality of sockets has an inverted pyramidal shape comprising at least three socket sidewalls, wherein each pin in the plurality of pins is respectively located in a respective socket in the plurality of sockets, each socket in the plurality of sockets has a sloped sidewall configured to converge at an apex in the substrate and a distal end of each pin in the plurality of pins abuts the sidewall of each socket in the plurality of sockets, wherein further the second die comprises a first conductive pad that is composed of a malleable material and that deforms when the first die is stacked on the second die such that the first conductive pad forms an electrically conductive path between the first die and the second die.

11. The IC of claim 10 , further comprising:
a standoff located between the first surface of the first die and the upper surface of the second die, wherein the standoff has a thickness configured to position a first component located in the first die a particular distance from a position of a second component located in the second die.

12. The IC of claim 11 , wherein the second component is a waveguide and the first component is a channel, wherein the channel locates an optical fiber and the channel is positioned such that light is transmitted between the waveguide and the optical fiber.

13. The IC of claim 11 , wherein the first component is a laser and the second component is a waveguide, the laser is positioned such that light transmitted from the laser is incident upon the waveguide.

14. The IC configuration of claim 1 , wherein the pin is formed on the first surface of the first chip such that the proximal end of the pin is attached to the first surface of the first chip.

15. The IC of claim 10 , wherein the first die comprises a second conductive pad that is composed of a malleable material and that deforms when the first die is stacked on the second die such that the second conductive pad forms a second electrically conductive path between the first die and the second die.

Assignees

• Nat Tech & Eng Solutions Sandia Llc

Inventors

• Burckel David Bruce
• Bauer Todd
• Henry Michael David
• Pomerene Andrew

Classifications

• G02B6/4231

  with intermediate elements, e.g. rods and balls, between the elements · CPC title

• G02B6/30 Primary

  for use between fibre and thin-film device · CPC title

• H01S5/3013

  AIIIBV compounds · CPC title

• H01S5/22

  having a ridge or stripe structure · CPC title

• G02B6/3636

  the mechanical coupling means being grooves (G02B6/3652 takes precedence) · CPC title