Unity gain buffer with two states

US10620299B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10620299-B2
Application numberUS-201715465562-A
CountryUS
Kind codeB2
Filing dateMar 21, 2017
Priority dateMar 21, 2017
Publication dateApr 14, 2020
Grant dateApr 14, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A unity gain buffer provides an “ON” state in which the input signal is coupled to the output terminal and an “OFF” state in which the input signal is isolated from the output terminal. Multiple unity gain buffers may share the same load to form a voltage-mode maximum follower or a multiplexer.

First claim

Opening claim text (preview).

I claim: 1. A multi-channel system having a plurality of signal channels, an individual signal channel configured to receive an input signal from a corresponding light sensor and comprising: a pre-amplifier, configured to receive the input signal and provide an amplified signal; and a buffer arrangement, configured to receive the amplified signal from the pre-amplifier and provide an output signal at an output terminal of the buffer arrangement, where the output terminals of the plurality of signal channels are coupled to a single output node. 2. The multi-channel system according to claim 1 , wherein the buffer arrangement comprises: a differential amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal; a transistor having a first terminal, a second terminal and a third terminal, wherein the first terminal of the transistor is coupled to a power supply voltage reference and the third terminal is coupled to the output terminal of the differential amplifier; and a diode matrix having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the diode matrix is coupled to the inverting input terminal of the differential amplifier, the second terminal of the diode matrix is coupled to the second terminal of the transistor, and the third terminal of the diode matrix is coupled to the output terminal of the buffer arrangement. 3. The multi-channel system according to claim 2 , wherein the buffer arrangement is configured such that (a) when the buffer arrangement is in a first state, the first and the second terminals of the diode matrix have a voltage difference that substantially equals a voltage drop across a conducting diode, and (b) when the buffer arrangement is in a second state, the first and the second terminals of the diode matrix have substantially the same voltage. 4. The multi-channel system according to claim 2 , wherein the buffer arrangement further includes a diode, coupled between the first and second terminals of the diode matrix. 5. The multi-channel system according to claim 2 , wherein the buffer arrangement further includes: a first diode, coupled between the third and first terminals of the diode matrix, and a second diode, couple between the third and second terminals of the diode matrix. 6. The multi-channel system according to claim 2 , wherein, the buffer arrangement further includes a current source, coupled between the power supply voltage reference and the first terminal of the diode matrix. 7. The multi-channel system according to claim 2 , wherein the buffer arrangement further includes a current source, coupled between the second terminal of the transistor and a ground reference. 8. The multi-channel system of claim 2 , wherein the buffer arrangement further includes a current source, coupled between a ground voltage reference and the third terminal of the diode matrix. 9. The multi-channel system according to claim 2 , wherein the transistor is a bipolar transistor. 10. The multi-channel system according to claim 1 , wherein the output terminals of the plurality of signal channels are coupled to the single output node such that the buffer arrangement forms a voltage follower circuit. 11. The multi-channel system according to claim 1 , wherein the buffer arrangement includes a plurality of diodes, and wherein configuring the plurality of diodes according to a first set of parameters configures the buffer arrangement to operate in a first state, and configuring the plurality of diodes according to a second set of parameters configures the buffer arrangement to operate in a second state. 12. The multi-channel system according to claim 11 , wherein, during operation of the multi-channel system, when the buffer arrangement of one of the plurality of signal channels operates in the first state, the buffer arrangement of each of remaining ones of the plurality of signal channels operate in the second state. 13. The multi-channel system according to claim 1 , where the multi-channel system is a multi-channel light detection and ranging (LIDAR) system. 14. The multi-channel system according to claim 13 , further comprising a plurality of light sensors, where the individual light signal channel is configured to receive the input signal from a different one of the plurality of light sensors. 15. The multi-channel system according to claim 14 , wherein the light sensors include avalanche photodiodes. 16. A system, comprising a buffer arrangement, the buffer arrangement comprising: a differential amplifier having a non-inverting input terminal, an inverting input terminal, and an output terminal; a transistor having a first terminal, a second terminal, and a third terminal, the first terminal of the transistor is coupled to a power supply voltage reference and the third terminal is coupled to the output terminal of the differential amplifier; and a diode matrix having a first terminal, a second terminal and a third terminal, wherein the first terminal of the diode matrix is coupled to the inverting input terminal of the differential amplifier, the second terminal of the diode matrix is coupled to the second terminal of the transistor, and the third terminal of the diode matrix is coupled to output terminal of the buffer arrangement. 17. The system according to claim 16 , wherein the buffer arrangement is configured such that (a) when the buffer arrangement is in a first state, the first and the second terminals of the diode matrix have a voltage difference that substantially equals a voltage drop across a conducting diode, and (b) when the buffer arrangement is in a second state, the first and the second terminals of the diode matrix have substantially the same voltage. 18. The system according to claim 16 , wherein the buffer arrangement further includes a diode, configured to connect the first and second terminals of the diode matrix. 19. The system according to claim 16 , wherein the buffer arrangement further includes: a first diode, configured to connect the third terminal of the diode matrix to the first terminal of the diode matrix, and a second diode, configured to connect the third terminal of the diode matric to the second terminal of diode matrix. 20. The system according to claim 16 , further comprising a current source, coupled to the first terminal of the diode matrix. 21. The system according to claim 16 , further comprising a current source, coupled to the second terminal of the transistor. 22. The system according to claim 16 , further comprising a current source, coupled to third terminal of the diode matrix. 23. The system according to claim 16 , wherein the transistor is a bipolar transistor. 24. The system according to claim 16 , where the system is a multi-channel light detection and ranging (LIDAR) system. 25. The system according to claim 24 , further comprising a light sensor, coupled to the buffer arrangement to provide a signal generated by the light sensor to the buffer arrangement. 26. The system according to claim 25 , wherein the light sensor is an avalanche photodiode.

Assignees

Inventors

Classifications

  • using bipolar transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

  • Circuits for detection, sampling, integration or read-out · CPC title

  • Differential amplifier with circuit arrangements to enhance the transconductance · CPC title

  • Controlling received signal intensity, gain or exposure of sensor · CPC title

  • using IC blocks as the active amplifying circuit · CPC title

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Frequently asked questions

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What does patent US10620299B2 cover?
A unity gain buffer provides an “ON” state in which the input signal is coupled to the output terminal and an “OFF” state in which the input signal is isolated from the output terminal. Multiple unity gain buffers may share the same load to form a voltage-mode maximum follower or a multiplexer.
Who is the assignee on this patent?
Linear Tech Corp
What technology area does this patent fall under?
Primary CPC classification G01S7/4816. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Apr 14 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).