Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator

Patent metadata

Field	Value
Publication number	US-10615810-B2
Application number	US-201715632063-A
Country	US
Kind code	B2
Filing date	Jun 23, 2017
Priority date	Jan 8, 2013
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

Embodiments of an integrated circuit (IC) comprising circuitry to determine settings for an injection-locked oscillator (ILO) are described. In some embodiments, an injection signal is generated based on a first clock edge of a reference clock signal, and is injected into an ILO. Next, one or more output signals of the ILO are sampled based on a second clock edge of the reference clock signal, and settings for the ILO are determined based on the samples. In some embodiments, a sequence of two or more time-to-digital (TDC) codes is generated based on a reference clock signal and a free-running ILO. In some embodiments, the TDC circuitry that is already present in a delay-locked loop is reused for determining the sequence of two or more TDC codes. The ILO settings can then be determined based on the sequence of two or more TDC codes.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a first injection-locked oscillator (ILO) to generate a set of oscillating signals having different phases, wherein the first ILO has a natural oscillation frequency, and wherein the first ILO generates the set of oscillating signals based on a reference clock signal having a reference clock frequency;
a time-to-digital (TDC) converter to generate a sequence of two or more codes by sampling at least one oscillating signal in the set of oscillating signals when the first ILO is oscillating at the natural oscillation frequency; and
a control circuit to determine settings for the first ILO based on the sequence of two or more codes, wherein the settings correspond to the natural oscillation frequency being substantially equal to the reference clock frequency or an integral multiple of the reference clock frequency.

2. The IC of claim 1 , wherein the settings for the ILO correspond to a delay setting for each delay element in the ILO.

3. The IC of claim 1 , comprising a second ILO to generate an output clock signal based on the reference clock signal, wherein the settings for the first ILO are provided to the second ILO.

4. The IC of claim 3 , comprising injection circuitry to inject the reference clock signal at an injection location in the second ILO that is selected based on the sequence of two or more codes.

5. The IC of claim 3 , wherein the injection circuitry comprises:
a de-multiplexer/de-blender, wherein the reference clock signal is provided as an input to the de-multiplexer/de-blender, and wherein outputs of the de-multiplexer/de-blender are injected into corresponding injection locations of the second ILO; and
circuitry to generate a select signal for the de-multiplexer/de-blender based on the sequence of two or more codes.

6. The IC of claim 3 , comprising a duty-cycle corrector to remove deterministic jitter from the output clock signal.

7. The IC of claim 6 , comprising an output buffer, wherein an output signal of the duty-cycle corrector is provided as a clock input to the output buffer.

8. A method, comprising:
generating a set of oscillating signals having different phases by using a first injection-locked oscillator (ILO), wherein the first ILO has a natural oscillation frequency, and wherein the set of oscillating signals is generated based on a reference clock signal having a reference clock frequency;
generating a sequence of two or more codes by using a time-to-digital (TDC) converter, wherein the sequence of two or more codes is generated by sampling at least one oscillating signal in the set of oscillating signals when the first ILO is oscillating at the natural oscillation frequency; and
determining settings for the first ILO based on the sequence of two or more codes, wherein the settings correspond to the natural oscillation frequency being substantially equal to the reference clock frequency or an integral multiple of the reference clock frequency.

9. The method of claim 8 , wherein the settings for the ILO correspond to a delay setting for each delay element in the ILO.

10. The method of claim 8 , comprising generating an output clock signal by using a second ILO, wherein the output clock signal is generated based on the reference clock signal, and wherein the settings for the first ILO are provided to the second ILO.

11. The method of claim 10 , comprising injecting the reference clock signal at an injection location in the second ILO that is selected based on the sequence of two or more codes.

12. The method of claim 10 , comprising removing deterministic jitter from the output clock signal.

13. The method of claim 12 , comprising driving a data signal based on the output clock signal.

14. The method of claim 8 , wherein the method is performed when one or more of the following events occur:
a clock drift in the reference clock signal is greater than a threshold,
a change in a temperature value is greater than a threshold, and
a change in a supply voltage value is greater than a threshold.

15. A method, comprising:
obtaining a set of samples by sampling a set of oscillating signals based on a reference clock signal having a reference clock frequency, wherein the set of oscillating signals is generated by a first injection-locked oscillator (ILO) having a natural oscillation frequency, and wherein each oscillating signal in the set of oscillating signals has a different phase;
determining a sequence of two or more codes, wherein each code in the sequence of two or more codes is determined based on a set of samples that was obtained when the set of oscillating signals was sampled at a clock edge of the reference clock signal, and wherein different codes in the sequence of two or more codes correspond to different clock edges of the reference clock signal that were used for sampling the set of oscillating signals; and
determining settings for the first ILO based on the sequence of two or more codes wherein the settings correspond to the natural oscillation frequency being substantially equal to the reference clock frequency or an integral multiple of the reference clock frequency.

16. The method of claim 15 , further comprising preventing an injection signal from being injected into the first ILO.

17. The method of claim 15 , wherein said determining includes determining a delay-element setting by performing a table lookup based on a value that is computed using the sequence of two or more codes.

18. The method of claim 15 , wherein the first ILO is part of a delay-locked loop (DLL), and wherein the method is performed after the DLL achieves a phase lock on the reference clock signal.

19. The method of claim 15 , wherein the method is performed when one or more of the following events occur:
a clock drift in the reference clock signal is greater than a threshold,
a change in a temperature value is greater than a threshold, and
a change in a supply voltage value is greater than a threshold.

20. The method of claim 15 , comprising generating an output clock signal by using a second ILO, wherein the output clock signal is generated based on the reference clock signal, and wherein the settings for the first ILO are provided to the second ILO.

Assignees

• Rambus Inc

Inventors

• Zerbe Jared L
• Hossain Masum

Classifications

• H03L1/00

  Stabilisation of generator output against variations of physical values, e.g. power supply · CPC title

• H03K3/0307

  Stabilisation of output, e.g. using crystal · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• H03L7/24 Primary

  using a reference signal directly applied to the generator · CPC title

• H03L7/083

  the reference signal being additionally directly applied to the generator · CPC title