Low power 25% duty cycle local oscillator clock generation circuit

Patent metadata

Field	Value
Publication number	US-10615780-B2
Application number	US-201715835861-A
Country	US
Kind code	B2
Filing date	Dec 8, 2017
Priority date	Dec 8, 2017
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.

First claim

What is claimed is:

1. A clock generation circuit for generating clock signals having a second duty cycle comprising a plurality of NAND gates each including:
a first input terminal;
a second input terminal;
an output terminal;
a first NMOS transistor having a drain of the first NMOS transistor coupled to the output terminal;
a second NMOS transistor having a drain of the second NMOS transistor coupled to a source of the first NMOS transistor and a source of the second NMOS transistor coupled to a ground;
a third NMOS transistor having a drain of the third NMOS transistor coupled to the output terminal;
a fourth NMOS transistor having a drain of the fourth NMOS transistor coupled to a source of the third NMOS transistor and a source of the fourth NMOS transistor coupled to the ground, wherein a gate of the first NMOS transistor and a gate of the fourth NMOS transistor couple to the first input terminal and a gate of the second NMOS transistor and a gate of the third NMOS transistor couple to the second input terminal; and
a PMOS transistor having a source of the PMOS transistor coupled to a supply voltage, a drain of the PMOS transistor coupled to the output terminal, and a gate of the PMOS transistor coupled to the first input terminal, wherein the output terminal and the supply voltage is configured to be decoupled when the PMOS transistor is turned off, wherein a logic state of a signal at the second input terminal does not affect the coupling of the first output terminal and the supply voltage.

2. The clock generation circuit of claim 1 , wherein the first input terminal of first one of the plurality of NAND gates is configured to couple to a first clock having a first duty cycle, and the second input terminal of the first one of the plurality of NAND gates is configured to couple to a second clock having the first duty cycle, wherein the second clock lags the first clock by 90 degrees in phase.

3. The clock generation circuit of claim 2 , wherein the first duty cycle is 50% and the second duty cycle is 25%.

4. The clock generation circuit of claim 2 , wherein the first input terminal of second one of the plurality of NAND gates is configured to couple to the second clock, and the second input terminal of the second one of the plurality of NAND gates is configured to couple to a third clock having the first duty cycle, wherein the third clock lags the second clock by 90 degrees in phase.

5. The clock generation circuit of claim 4 , wherein the first input terminal of third one of the plurality of NAND gates is configured to couple to the third clock, and the second input terminal of the third one of the plurality of NAND gates is configured to couple to a fourth clock having the first duty cycle, wherein the third clock lags the second clock by 90 degrees in phase.

6. The clock generation circuit of claim 5 , wherein the first input terminal of fourth one of the plurality of NAND gates is configured to couple to the fourth clock, and the second input terminal of the fourth one of the plurality of NAND gates is configured to couple to the first clock.

7. The clock generation circuit of claim 1 further comprising a plurality of inverters each coupled to one of the plurality of NAND gates.

8. The clock generation circuit of claim 7 further comprising one or more mixers coupled to the plurality of inverters.

9. The clock generation circuit of claim 1 further comprising a plurality of inverters each coupled to one of the plurality of NAND gates.

10. The clock generation circuit of claim 1 is configured to received four input clock signals each having 50% duty cycle and generate four output clock signals each having 25% duty cycle, wherein a second of four input clock signals lags a first of four input clocks by 90 degrees in phase, a third of four input clock signals lags the second of four input clocks by 90 degrees in phase, and a fourth of four input clock signals lags the third of four input clocks by 90 degrees in phase, and wherein
a first one of the plurality of NAND gates is configured to couple the first terminal of the first one of the plurality of NAND gates with the first of four input clocks and couple the second terminal of the first one of the plurality of NAND gates with the second of four input clocks;
a second one of the plurality of NAND gates is configured to couple the first terminal of the second one of the plurality of NAND gates with the second of four input clocks and couple the second terminal of the second one of the plurality of NAND gates with the third of four input clocks;
a third one of the plurality of NAND gates is configured to couple the first terminal of the third one of the plurality of NAND gates with the third of four input clocks and couple the second terminal of the third one of the plurality of NAND gates with the fourth of four input clocks; and
a fourth one of the plurality of NAND gates is configured to couple the first terminal of the fourth one of the plurality of NAND gates with the fourth of four input clocks and couple the second terminal of the fourth one of the plurality of NAND gates with the first of four input clocks.

Assignees

• Qualcomm Inc

Inventors

• Paul Animesh
• Chen Xinhua

Classifications

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03D7/1466

  Passive mixer arrangements · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03K2005/00234

  using circuits having two logic levels · CPC title

• H03K5/023

  using field effect transistors · CPC title