Transistor array substrate and display panel using the same

Patent metadata

Field	Value
Publication number	US-10615262-B2
Application number	US-201715443411-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Mar 2, 2016
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A display panel comprises a first substrate, a second substrate, a display layer and transistors. One of the transistors includes a gate electrode disposed on the base plate, a first insulating layer disposed on the gate electrode, an active layer disposed on the first insulating layer, and a source electrode and a drain electrode disposed on the active layer, wherein the active layer includes a channel region between the source electrode and the drain electrode. At least one of the source and drain electrodes includes a first conductive layer disposed on the active layer, and a second conductive layer disposed on and contacting the first conductive layer, wherein the second conductive layer exposes a portion of top surface of the first conductive layer so that the first conductive layer possesses a first protrusion portion protruding from the edge of the second conductive layer and extending towards the channel region.

First claim

What is claimed is:

1. A display panel, comprising:
a first substrate including a base plate;
a second substrate disposed opposite to the first substrate;
a display layer disposed between the first substrate and the second substrate; and
a plurality of transistors disposed between the base plate and the display layer, wherein one of the plurality of transistors comprises:
a gate electrode, disposed on the base plate;
a first insulating layer, disposed on the gate electrode;
an active layer, disposed on the first insulating layer, and the active layer having a channel region;
a source electrode and a drain electrode disposed on the active layer; and
a second insulating layer disposed on the source electrode and the drain electrode, wherein at least one of the source electrode and the drain electrode comprising:
a first conductive layer, disposed on the active layer; and
a second conductive layer, disposed on the first conductive layer, wherein
the second conductive layer comprises copper;
wherein the first conductive layer includes a first protrusion portion exposed by the second conductive layer, and the first protrusion portion has a first bottom surface and a first sidewall, and
wherein the first bottom surface contacts the active layer, and the first sidewall contacts the second insulating layer;
wherein the second conductive layer has a second sidewall and a second bottom surface, the second sidewall is adjacent to the channel region, wherein an angle θ 1 between the first sidewall and the first bottom surface is greater than an angle θ 2 between the second sidewall and the second bottom surface.

2. The display panel according to claim 1 , wherein a length of the first protrusion portion is equal to or less than 0.36 μm.

3. The display panel according to claim 1 , wherein a length of the first protrusion portion is ranged from 20% to 100% of a thickness of the second conductive layer.

4. The display panel according to claim 1 , wherein the gate electrode comprises a lower conductive layer disposed on the base plate, and an upper conductive layer disposed on the lower conductive layer, wherein the lower conductive layer includes a second protrusion portion protruding from an edge of the upper conductive layer, and the second protrusion portion has a top surface exposed by the upper conductive layer.

5. The display panel according to claim 4 , wherein a first length of the first protrusion portion is greater than a second length of the second protrusion portion.

6. The display panel according to claim 4 , wherein the second insulating layer is silicon oxide.

7. The display panel according to claim 1 , wherein an outer edge of the active layer extends beyond an outer edge of the gate electrode.

8. The display panel according to claim 1 , wherein at least one of the source electrode and the drain electrode covers a portion of a lateral surface of the active layer.

9. The display panel according to claim 1 , wherein the first conductive layer covers a portion of a lateral surface of the active layer.

10. The display panel according to claim 1 , wherein the second conductive layer has a second sidewall and a second bottom surface, the first sidewall and the second sidewall are adjacent to the channel region, and an angle between the first sidewall and the first bottom surface is different from an angle between the second sidewall and the second bottom surface.

11. A transistor array substrate, comprising:
a base plate; and
a plurality of transistors disposed on the base plate, and one of the plurality of transistors comprising:
a gate electrode, disposed on the base plate;
a first insulating layer, disposed on the gate electrode;
an active layer, disposed on the first insulating layer, and the active layer having a channel region;
a source electrode and a drain electrode disposed on the active layer; and
a second insulating layer disposed on the source electrode and the drain electrode, wherein at least one of the source electrode and the drain electrode comprising:
a first conductive layer, disposed on the active layer; and
a second conductive layer, disposed on the first conductive layer, wherein
the second conductive layer comprises copper;
wherein the first conductive layer includes a first protrusion portion exposed by the second conductive layer, and the first protrusion portion has a first bottom surface and a first sidewall, and
wherein the first bottom surface contacts the active layer, and the first sidewall contacts the second insulating layer;
wherein the second conductive layer has a second sidewall and a second bottom surface, the second sidewall is adjacent to the channel region, wherein an angle θ 1 between the first sidewall and the first bottom surface is greater than an angle θ 2 between the second sidewall and the second bottom surface.

12. The transistor array substrate according to claim 11 , wherein a length of the first protrusion portion is equal to or less than 0.36 μm.

13. The transistor array substrate according to claim 11 , wherein a length of the first protrusion portion is ranged from 20% to 100% of a thickness of the second conductive layer.

14. The transistor array substrate according to claim 11 , wherein the gate electrode comprises a lower conductive layer disposed on the base plate and an upper conductive layer disposed on the lower conductive layer, wherein the lower conductive layer includes a second protrusion portion protruding from an edge of the upper conductive layer, and the second protrusion portion has a top surface exposed by the upper conductive layer.

15. The transistor array substrate according to claim 14 , wherein a first length of the first protrusion portion is greater than a second length of the second protrusion portion.

16. The transistor array substrate according to claim 11 , wherein an outer edge of the active layer extends beyond an outer edge of the gate electrode.

17. The transistor array substrate according to claim 11 , wherein at least one of the source electrode and the drain electrode covers a portion of a lateral surface of the active layer.

18. The transistor array substrate according to claim 11 , wherein the first conductive layer covers a portion of a lateral surface of the active layer.

Assignees

• Innolux Corp

Inventors

• Lin Chun-Liang
• Tsuei Bo-Chin
• Chen Hung-Kun
• Hsu Nai-Fang
• Chen Yi-Ching

Classifications

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H01L29/41733 Primary

  Electricity · mapped topic

• H01L29/41775

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic