Structure having isolated deep substrate vias with decreased pitch and increased aspect ratio and related method

Patent metadata

Field	Value
Publication number	US-10615072-B2
Application number	US-201815967449-A
Country	US
Kind code	B2
Filing date	Apr 30, 2018
Priority date	Oct 24, 2014
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A structure having isolated deep substrate vias with decreased pitch and increased aspect ratio is disclosed. The structure includes a device layer over a buried oxide layer, a deep trench extending through the device layer, a dielectric filler in the deep trench, via holes in the dielectric filler, and conductive fillers in the via holes being the isolated deep substrate vias. The dielectric filler may include silicon oxide. The conductive fillers may include tungsten or copper. An adjacent pair of the isolated deep substrate vias within the deep trench has a pitch equal to or less than 1.0 microns.

First claim

The invention claimed is:

1. A structure comprising:
a device layer over a buried oxide layer, wherein a field effect transistor (FET) is fabricated in the device layer, the FET including a source, a drain and a gate located at a first surface of the device layer, and wherein the buried oxide layer is located at a second surface of the device layer, opposite the first surface;
an isolation region formed in the device layer from the first surface, wherein the isolation region electrically isolates the FET in the device layer;
an insulative layer formed over the FET and the isolation region;
a deep trench extending entirely through said insulative layer, said isolation region and said device layer to said buried oxide layer;
a dielectric filler that fills said deep trench and extends over the insulative layer;
a plurality of via holes in said dielectric filler, said plurality of via holes extending through said dielectric filler and said buried oxide layer;
a conductive filler located in each of said plurality of via holes, wherein each conductive filler forms an isolated deep substrate via that extends through said dielectric filler and said buried oxide layer, wherein a portion of each conductive filler is exposed through the buried oxide layer at a bottom surface of the structure; and
contacts that extend through the dielectric filler and the insulative layer to contact the FET.

2. The structure of claim 1 further comprising a dielectric liner in each of said plurality of via holes and surrounding each conductive filler.

3. The structure of claim 2 wherein each said dielectric liner comprises tetraethylorthosilicate (TEOS).

4. The structure of claim 1 further comprising a dielectric liner lining said deep trench.

5. The structure of claim 1 wherein said dielectric filler comprises silicon oxide.

6. The structure of claim 1 wherein said conductive filler comprises tungsten or copper.

7. The structure of claim 1 wherein said device layer comprises silicon.

8. The structure of claim 1 , further comprising:
a first dielectric liner in said deep trench; and
a second dielectric liner in said plurality of via holes.

9. The structure of claim 8 , wherein the dielectric filler, first dielectric liner and buried oxide layer have substantially similar compositions.

10. The structure of claim 9 , wherein the dielectric filler comprises silicon oxide, the first dielectric liner comprises tetraethylorthosilicate (TEOS) and the buried oxide layer comprises silicon oxide.

11. The structure of claim 1 , wherein the device layer is silicon having a thickness of at least 1.0 microns.

12. The structure of claim 1 , wherein each deep substrate via has an aspect ratio equal to or greater than 5:1.

13. The structure of claim 1 , wherein said deep trench extends through said device layer and terminates on a top surface of said buried oxide layer.

14. The structure of claim 1 , wherein the conductive filler forms an adjacent pair of isolated deep substrate vias within said deep trench, wherein said adjacent pair of deep substrate vias has a pitch equal to or less than 1.0 microns.

15. The structure of claim 1 wherein said deep trench extends through said device layer and partially through said buried oxide layer.

Assignees

• Newport Fab Llc

Inventors

• Kar-Roy Arjun
• Howard David J

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H01L2924/0002

  Electricity · mapped topic