Memory system for controlling read voltage using cached data and operation method of the same

Patent metadata

Field	Value
Publication number	US-10614880-B2
Application number	US-201715831979-A
Country	US
Kind code	B2
Filing date	Dec 5, 2017
Priority date	Feb 20, 2017
Publication date	Apr 7, 2020
Grant date	Apr 7, 2020

Abstract

A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

First claim

What is claimed is:

1. A memory system, comprising:
a memory device including a cell array and a read and write circuit suitable for reading and writing data from and to the cell array; and
a memory controller including:
a cache memory suitable for caching a portion of a-data stored in the memory device; and
a read voltage controller suitable for controlling a level of a read voltage used for a read operation of the memory device by comparing cache data cached in the cache memory with data corresponding to the cache data, read from the cell array through the read and write circuit,
wherein the cache data is data formerly read from the cell array and the data corresponding to the cache data is data newly read from the cell array.

2. The memory system of claim 1 , wherein the read voltage controller controls the level of the read voltage based on the number of different bits between the cache data and the data read from the cell array.

3. The memory system of claim 2 , wherein the read voltage controller controls the level of the read voltage in such a manner that the number of the different bits is decreased.

4. The memory system of claim 1 , wherein the memory controller further includes:
a host interface suitable for communicating with a host;
a scheduler suitable for determining a process order of requests received from the host;
a command generator suitable for generating a command to be applied to the memory device; and
a memory interface suitable for communicating with the memory device.

5. A method for operating a memory system, comprising:
reading a cached data from a cache memory included in a memory controller;
reading data corresponding to the cached data from a cell array of a memory device through a read and write circuit of the memory device;
comparing the cached data with the data read from the cell array; and
determining a level of a read voltage used for a read operation of the memory device based on the comparison result,
wherein the cached data is data formerly read from the cell array and the data corresponding to the cache data is data newly read from the cell array.

6. The method of claim 5 , wherein the determining of the level of the read voltage of the memory device based on the comparison result includes:
determining whether or not the number of different bits between the cached data and the data read from the cell array is equal to or greater than a threshold value; and
when it is determined that the number of the different bits between the cached data and the data read from the cell array is equal to or greater than the threshold value, controlling the level of the read voltage.

7. The method of claim 6 , wherein the controlling of the level of the read voltage includes
increasing or decreasing the level of the read voltage such that the number of the different bits is made to be less than the threshold value.

8. The method of claim 6 , wherein the controlling of the level of the read voltage includes:
increasing the level of the read voltage;
re-reading the data from the cell array by using the read voltage whose level is increased;
re-checking whether or not the number of the different bits is less than the threshold value; and
when the number of the different bits is equal to or greater than the threshold value, repeatedly performing the increasing of the level of the read voltage, the re-reading of the data from the cell array, and the re-checking of whether or not the number of the different bits is less than the threshold value.

9. The method of claim 6 , wherein the controlling of the level of the read voltage includes:
decreasing the level of the read voltage;
re-reading the data from the cell array by using the read voltage level which is decreased;
re-checking whether or not the number of the different bits is less than the threshold value; and
when the number of the different bits is equal to or greater than the threshold value, repeatedly performing the decreasing of the level of the read voltage, the re-reading of the data from the cell array corresponding to the cached data from the memory device, and the re-checking of whether or not the number of the different bits is less than the threshold value.

10. The method of claim 6 , wherein the controlling of the level of the read voltage includes:
increasing the level of the read voltage;
re-reading the data corresponding to the cached data from the cell array by using the read voltage level which is increased;
checking whether or not the number of the different bits is decreased; and
when the number of the different bits is decreased, increasing the level of the read voltage until the number of the different bits becomes less than the threshold value.

11. The method of claim 10 , wherein the controlling of the level of the read voltage further includes:
when the number of the different bits is not decreased, decreasing the level of the read voltage until the number of the different bits becomes less than the threshold value.

12. The method of claim 6 , wherein the controlling of the level of the read voltage includes:
decreasing the level of the read voltage;
re-reading the data from the cell array by using the read voltage level which is decreased;
checking whether or not the number of the different bits is decreased; and
when the number of the different bits is decreased, decreasing the level of the read voltage until the number of the different bits becomes less than the threshold value.

13. The method of claim 12 , wherein the controlling of the level of the read voltage further includes:
when the number of the different bits is not decreased, increasing the level of the read voltage until the number of the different bits becomes less than the threshold value.

14. A memory system, comprising:
a memory device including a cell array and a read and write circuit suitable for reading and writing data from and to the cell array, the cell array including a plurality of regions; and
a memory controller including:
a cache memory suitable for caching a portion of data stored in each of the plurality of the regions of the memory device; and
a read voltage controller suitable for controlling a level of a read voltage used for a read operation on each of the plurality of the regions by comparing cache data corresponding to each of the plurality of regions, cached in the cache memory with a portion of data corresponding to the cache data, read from each of the plurality of the regions in the cell array through the read and write circuit,
wherein the cache data is data formerly read from the cell array and the data correspond to the cache data is data newly read from the cell array.

Assignees

• Sk Hynix Inc

Inventors

• JO Sang-Gu
• Kwon Jung-Hyun
• Lee Sung-Eun
• Kim Yong-Ju

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title