Remote direct memory access in computing systems
US-2019079897-A1 · Mar 14, 2019 · US
US10614028B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10614028-B2 |
| Application number | US-201715824914-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 28, 2017 |
| Priority date | Sep 14, 2017 |
| Publication date | Apr 7, 2020 |
| Grant date | Apr 7, 2020 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
Distributed computing systems, devices, and associated methods of packet routing are disclosed herein. In one embodiment, a method includes receiving, from a computing network, a packet at a packet processor of a server. The method also includes matching the received packet with a flow in a flow table contained in the packet processor and determining whether the action indicates that the received packet is to be forwarded to a NIC buffer in the outbound processing path of the packet processor instead of the NIC. The method further includes in response to determining that the action indicates that the received packet is to be forwarded to the NIC buffer, forwarding the received packet to the NIC buffer and processing the packet in the NIC buffer to forward the packet to the computer network without exposing the packet to the main processor.
Opening claim text (preview).
We claim: 1. A method for routing network traffic in a distributed computing system having a plurality of hosts interconnected by a computer network, the individual hosts having a main processor, a network interface card (“NIC”), and a hardware packet processor operatively coupled to one another, the method comprising: receiving, from the computing network, a packet at the packet processor of a host, the packet processor including an inbound processing path and an outbound processing path in opposite processing directions; matching the received packet with a flow in a flow table contained in the packet processor following the inbound processing path of the packet processor, the flow being associated with an action in the flow table; determining whether the action indicates that the received packet is to be forwarded to a NIC buffer in the outbound processing path of the packet processor instead of the NIC; and in response to determining that the action indicates that the received packet is to be forwarded to the NIC buffer, forwarding the received packet to the NIC buffer; and processing the packet in the NIC buffer following the outbound processing path to forward the packet to the computer network without exposing the packet to the main processor, thereby reducing network latency associated with the packet by avoiding software processing of the packet utilizing the main processor of the host. 2. The method of claim 1 wherein: the inbound processing path includes a parser, a lookup circuit, and an action circuit operatively coupled to one another in sequence; and matching the received packet includes: parsing a header of the received packet with the parser; matching at least a portion of the parsed header with an entry in the flow table; and identifying the action as indicated by the entry in the flow table. 3. The method of claim 1 wherein: the inbound processing path includes an action circuit configured to perform the action, the action circuit having a first output to the NIC buffer and a second output to the NIC; and forwarding the received packet to the NIC buffer includes selectively forwarding the received packet to the NIC buffer via the first output of the action circuit in the inbound processing path. 4. The method of claim 1 wherein: the inbound processing path includes an action circuit configured to perform the action, the action circuit having a first output to the NIC buffer and a second output to the NIC; and the method further includes in response to determining that the action indicates that the received packet is to be forwarded to the NIC instead of the NIC buffer, forwarding the received packet to the NIC via the second output of the action circuit. 5. The method of claim 1 wherein: the outbound processing path includes an outbound multiplexer operatively coupled to the NIC buffer, the outbound multiplexer being configured to process input from the NIC buffer in a round-a-robin fashion; and processing the packet in the NIC buffer includes retrieving the packet from the NIC buffer using the outbound multiplexer and processing the retrieved packet following the outbound processing path. 6. The method of claim 1 wherein: the outbound processing path includes an outbound multiplexer operatively coupled to the NIC buffer and an outbound packet buffer configured to receive an outbound packet from the NIC, the outbound multiplexer being configured to process input from the NIC buffer and the outbound packet buffer in a round-a-robin fashion; and processing the packet in the NIC buffer includes selectively retrieving the packet from the NIC buffer using the outbound multiplexer and processing the retrieved packet following the outbound processing path. 7. The method of claim 1 wherein: receiving the packet includes receiving the packet at the packet processor via a switch in the computer network; and processing the packet in the NIC buffer include processing the packet in the NIC buffer following the outbound processing path to forward the packet to the computer network via the same switch. 8. A method for routing network traffic in a distributed computing system having a plurality of hosts interconnected by a computer network, the individual hosts having a main processor, a network interface card (“NIC”), and a hardware packet processor operatively coupled to one another, the method comprising: receiving, at the packet processor, a packet generated by a first virtual machine on the host and destined to a second virtual machine on the same host in the distributed computing system, the packet processor including an inbound processing path and an outbound processing path in opposite processing directions; matching the received packet with a flow in a flow table contained in the packet processor following the outbound processing path of the packet processor, the flow being associated with an action in the flow table; determining whether the action indicates that the received packet is to be forwarded to a buffer in the inbound processing path of the packet processor instead of a switch in the computer network; and in response to determining that the action indicates that the received packet is to be forwarded to the buffer, forwarding the received packet to the buffer; and processing the packet in the buffer following the inbound processing path to forward the packet to the second virtual machine without exposing the packet to the switch in the computer network, thereby enabling network communications between the first and second virtual machines on the same host by avoiding exposing the packet to the switch. 9. The method of claim 8 wherein: the outbound processing path includes a parser, a lookup circuit, and an action circuit operatively coupled to one another in sequence; and matching the received packet includes: parsing a header of the received packet with the parser; matching at least a portion of the parsed header with an entry in the flow table; and identifying the action as indicated by the entry in the flow table. 10. The method of claim 8 wherein: the outbound processing path includes an action circuit configured to perform the action, the action circuit having a first output to the buffer and a second output to the switch; and forwarding the received packet to the buffer includes selectively forwarding the received packet to the buffer via the first output of the action circuit in the outbound processing path. 11. The method of claim 8 wherein: the outbound processing path includes an action circuit configured to perform the action, the action circuit having a first output to the buffer and a second output to the switch; and the method further includes in response to determining that the action indicates that the received packet is to be forwarded to the switch instead of the buffer, forwarding the received packet to the switch via the second output of the action circuit. 12. The method of claim 8 wherein: the inbound processing path includes an inbound multiplexer operatively coupled to the buffer, the inbound multiplexer being configured to process input from the buffer in a round-a-robin fashion; and processing the packet in the buffer includes retrieving the packet from the buffer using the inbound multiplexer and processing the retrieved packet following the inbound processing path. 13. The method of claim 8 wherein: the inbound processing path includes an inbound multiplexer operatively coupled to the buffer and an inbound packet buffer configured to receive an inbound packet from the switch, the inbound multiplexer being configured to process input from t
ensuring sequence integrity, e.g. using sequence numbers · CPC title
Network integration; Enabling network access in virtual machine instances · CPC title
Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields · CPC title
Hypervisor-specific management and integration aspects · CPC title
Virtual queuing · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.