Substrate for a temperature-compensated surface acoustic wave device or volume acoustic wave device

Patent metadata

Field	Value
Publication number	US-10608610-B2
Application number	US-201616064419-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Dec 22, 2015
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising a support substrate and an piezoelectric layer on the support substrate, wherein the support substrate comprises a semiconductor layer on a stiffening substrate having a coefficient of thermal expansion that is closer to the coefficient of thermal expansion of the material of the piezoelectric layer than that of silicon, the semiconductor layer being arranged between the piezoelectric layer and the stiffening substrate.

First claim

The invention claimed is:

1. A substrate for a surface acoustic wave device or bulk acoustic wave device, comprising:
a support substrate comprising a semiconductor layer on a stiffening substrate; and
a piezoelectric layer on the support substrate, the semiconductor layer disposed between the piezoelectric layer and the stiffening substrate, wherein the stiffening substrate has a coefficient of thermal expansion closer to a coefficient of thermal expansion of a material of the piezoelectric layer than that of silicon;
a dielectric layer between the piezoelectric layer and the semiconductor layer; and
a charge trapping layer at an interface between the dielectric layer and the semiconductor layer and/or an interface between the dielectric layer and the piezoelectric layer.

2. The substrate of claim 1 , wherein the stiffening substrate comprises sapphire, glass and/or spinel (MgAl 2 O 4 ).

3. The substrate of claim 2 , wherein the semiconductor layer comprises a material selected from the group consisting of: silicon, germanium, SiGe, SiC, and a III-V material.

4. The substrate of claim 3 , wherein the semiconductor layer comprises at least one electronic component.

5. The substrate of claim 4 , wherein the electronic component comprises a component selected from the group consisting of: a CMOS transistor, a switch, and a power amplifier.

6. The substrate of claim 5 , wherein a ratio of a thickness of the piezoelectric layer to a thickness of the stiffening substrate is less than or equal to 0.125.

7. The substrate of claim 6 , wherein the thickness of the piezoelectric layer is less than 50 μm, and the thickness of the stiffener substrate is between 400 and 800 μm.

8. The substrate of claim 7 , wherein the charge trapping layer comprises a layer of polycrystalline silicon.

9. The substrate of claim 5 , wherein a ratio of a thickness of the piezoelectric layer to a thickness of the stiffening substrate is less than or equal to 0.125.

10. A surface acoustic wave device, comprising:
the substrate of claim 1 ; and
two interdigitated metallic comb electrodes on a surface of the piezoelectric layer.

11. A bulk acoustic wave device, comprising:
the substrate of claim 1 ; and
two electrodes located respectively on opposing sides of the piezoelectric layer.

12. The substrate of claim 1 , wherein the stiffening substrate comprises sapphire, glass and/or spinel (MgAl 2 O 4 ).

13. The substrate of claim 1 , wherein the semiconductor layer comprises a material selected from the group consisting of: silicon, germanium, SiGe, SiC, and a III-V material.

14. The substrate of claim 1 , wherein the semiconductor layer comprises at least one electronic component.

15. The substrate of claim 1 , wherein a thickness of the piezoelectric layer is less than 50 μm, and a thickness of the stiffener substrate is between 400 and 800 μm.

16. The substrate of claim 15 , wherein a thickness of the piezoelectric layer is less than 1 μm.

17. Method of manufacturing a substrate for a surface acoustic wave device or bulk acoustic wave device, comprising:
transferring a semiconductor layer from a first donor substrate onto a stiffening substrate to form a support substrate;
forming a dielectric layer over the semiconductor layer;
transferring a piezoelectric layer onto the support substrate from a second donor substrate such that material of the dielectric layer and the semiconductor layer are disposed between the piezoelectric layer and the stiffening substrate, wherein the stiffening substrate has a coefficient of thermal expansion closer to a coefficient of thermal expansion of a material of the piezoelectric layer than that of silicon; and
forming a charge trapping layer at an interface between the dielectric layer and the semiconductor layer and/or an interface between the dielectric layer and the piezoelectric layer.

18. The method of claim 17 , wherein at least one of the transfer steps comprises the following sub-steps:
forming an embrittlement zone in the first or second donor substrate, respectively, by implantation of atomic species;
bonding the first or second donor substrate, respectively, onto the stiffener substrate or semiconductor layer, respectively; and
detaching the first or second substrate, respectively, along the embrittlement zone.

Assignees

• Soitec Silicon On Insulator

Inventors

• Broekaart Marcel
• Barge Thierry
• Guenard Pascal
• Radu Ionut
• Desbonnets Eric
• Kononchuk Oleg

Classifications

• H03H9/13

  for networks consisting of piezoelectric or electrostrictive materials (for networks using surface acoustic waves H03H9/145) · CPC title

• H03H9/17

  having a single resonator (crystal tuning forks H03H9/21) · CPC title

• H03H3/02

  for the manufacture of piezoelectric or electrostrictive resonators or networks (H03H3/08 takes precedence) · CPC title

• H03H9/145

  for networks using surface acoustic waves · CPC title

• H03H9/56

  Monolithic crystal filters · CPC title