Variable gain circuit and transimpedance amplifier using the same

Patent metadata

Field	Value
Publication number	US-10608599-B2
Application number	US-201816101102-A
Country	US
Kind code	B2
Filing date	Aug 10, 2018
Priority date	Aug 14, 2017
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A transimpedance amplifier includes a variable gain circuit configured to generate a pair of complementary signals in accordance with an input signal and a reference signal. A first differential circuit of the variable gain circuit includes a first transistor including a control terminal to receive the input signal, a second transistor including a control terminal to receive the reference signal, and a variable resistance circuit including a first field effect transistor (FET) and a second FET. A first timing when a voltage of a first linearity adjustment signal input to the first FET reaches a first threshold voltage of the first FET and a second timing when a voltage of a second linearity adjustment signal input to the second FET reaches a second threshold voltage of the second FET are different from each other.

First claim

What is claimed is:

1. A transimpedance amplifier, comprising:
a variable gain circuit configured to generate a pair of complementary signals in accordance with an input signal and a reference signal, the complementary signals including a first complementary signal and a second complementary signal; and
a linearity control circuit configured to generate a plurality of linearity adjustment signals to secure linearity of the variable gain circuit,
wherein the variable gain circuit includes
a first current source configured to supply a first current,
a second current source configured to supply a second current,
a first differential circuit configured to divide each of the first current and the second current into two parts in accordance with the input signal and the reference signal to generate a first current signal and a second current signal,
a first load element configured to generate the first complementary signal based at least in part on the first current signal, and
a second load element configured to generate the second complementary signal based at least in part on the second current signal,
wherein the first differential circuit includes
a first transistor including a control terminal to receive the input signal, a first current terminal to be electrically connected to the first current source, and a second current terminal to output the first current signal,
a second transistor including a control terminal to receive the reference signal, a first current terminal to be electrically connected to the second current source, and a second current terminal to output the second current signal, and
a variable resistance circuit including a plurality of field effect transistors, each of the field effect transistors being configured with a gate such that the linearity adjustment signals are input to the gates one-to-one, a source that is commonly connected to the first current terminal of the first transistor, and a drain that is commonly connected to the first current terminal of the second transistor,
wherein the variable resistance circuit has a combined resistance value which is obtained by combining respective resistance values of the field effect transistors,
wherein the linearity control circuit supplies the plurality of the linearity adjustment signals to the plurality of field effect transistors such that the combined resistance value becomes larger as an amplitude of the input signal or an amplitude of the pair of complementary signals is larger,
wherein each field effect transistor has a threshold voltage which is a voltage of the linearity adjustment signals for switching from an OFF state for electrically disconnecting the drain and the source thereof to an ON state for electrically connecting the drain and the source thereof,
wherein the plurality of field effect transistors includes a first field effect transistor and a second field effect transistor, and
wherein the plurality of the linearity adjustment signals includes a first linearity adjustment signal input to the first field effect transistor and a second linearity adjustment signal input to the second field effect transistor, the first linearity adjustment signal having a first timing when a voltage of the first linearity adjustment signal reaches a first threshold voltage of the first field effect transistor, the second linearity adjustment signal having a second timing when a voltage of the second linearity adjustment signal reaches a second threshold voltage of the second field effect transistor, the first timing and the second timing being different from each other.

2. The transimpedance amplifier according to claim 1 ,
wherein the voltage of the first linearity adjustment signal is larger than the voltage of the second linearity adjustment signal.

3. The transimpedance amplifier according to claim 1 ,
wherein the first threshold voltage is smaller than the second threshold voltage.

4. The transimpedance amplifier according to claim 1 ,
wherein a resistance value in an ON state of the first field effect transistor is larger than a resistance value in an ON state of the second field effect transistor.

5. The transimpedance amplifier according to claim 1 , further comprising:
a gain control circuit configured to generate a gain adjustment signal in order to adjust a gain of the variable gain circuit,
wherein the variable gain circuit further includes
a second differential circuit configured to divide the first current signal into a third current signal and a fourth current signal in accordance with the gain adjustment signal, and
a third differential circuit configured to divide the second current signal into a fifth current signal and a sixth current signal in accordance with the gain adjustment signal,
wherein the second current terminal of the first transistor is electrically connected to the second differential circuit,
wherein the second current terminal of the second transistor is electrically connected to the third differential circuit,
wherein the first load element converts the fourth current signal into the first complementary signal, and
wherein the second load element converts the sixth current signal into the second complementary signal.

6. The transimpedance amplifier according to claim 5 ,
wherein the gain control circuit includes an amplitude detection circuit configured to detect amplitude of the pair of complementary signals and a generation circuit configured to generate the gain adjustment signal based at least in part on the amplitude.

7. A variable gain circuit for generating a pair of complementary signals including a first complementary signal and a second complementary signal in accordance with an input signal and a reference signal, comprising:
a first current source configured to supply a first current;
a second current source configured to supply a second current;
a first differential circuit configured to divide each of the first current and the second current into two parts in accordance with the input signal and the reference signal to generate a first current signal and a second current signal;
a first load element configured to generate the first complementary signal based at least in part on the first current signal; and
a second load element configured to generate the second complementary signal based at least in part on the second current signal,
wherein the first differential circuit includes
a first transistor including a control terminal to receive the input signal, a first current terminal to be electrically connected to the first current source, and a second current terminal to output the first current signal,
a second transistor including a control terminal to receive the reference signal, a first current terminal to be electrically connected to the second current source, and a second current terminal to output the second current signal, and
a variable resistance circuit including a plurality of field effect transistors, each of the field effect transistors being configured such that a source is commonly connected to the first current terminal of the first transistor, and a drain is commonly connected to the first current terminal of the second transistor,
wherein the variable resistance circuit has a combined resistance value which is obtained by combining resistance values of the plurality of field effect transistors,
wherein each field effect transistor receives one of a plurality of linearity adjustment signals at a gate thereof, one-to-one,
wherein each field effect transistor has a threshold voltage which is a voltage of the linearity adjustment signals for switching from an OFF state for electrically disconnecting the drain and the source thereof to an ON state for electrically connecting the drain and th

Assignees

• Sumitomo Electric Industries

Inventors

• Sugimoto Yoshiyuki
• Itabashi Naoki

Classifications

• H03F3/45973

  by using a feedback circuit · CPC title

• H03F3/082 Primary

  with FET's (H03F3/085 takes precedence) · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03G1/0035

  using continuously variable impedance elements · CPC title

• H03G3/3084

  in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves (H03G3/32, H03G3/34 take precedence) · CPC title