Amplifiers and related integrated circuits

US10608588B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10608588-B2
Application numberUS-201715854034-A
CountryUS
Kind codeB2
Filing dateDec 26, 2017
Priority dateDec 26, 2017
Publication dateMar 31, 2020
Grant dateMar 31, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of an amplifiers and integrated circuits include a first transistor and a second transistor. A second current-carrying terminal of the first transistor may be coupled to a first current-carrying terminal of the second transistor and the control terminal of the second transistor may be coupled to a low impedance alternating current (AC) potential node. A bias network that includes a first circuit element and a second circuit element couples the second current-carrying terminal of the second transistor to the control terminal of the second transistor. The first circuit element may be configured to apply a portion of a potential at the second current-carrying terminal of the second transistor to the control terminal of the second transistor, and the second circuit element may be coupled between the control terminal of the second transistor and a fixed potential.

First claim

Opening claim text (preview).

What is claimed is: 1. An amplifier comprising: a first transistor that includes a first current-carrying terminal, a second current-carrying terminal, and a control terminal; a second transistor that includes a first current-carrying terminal, a second current-carrying terminal, and a control terminal, wherein the second current-carrying terminal of the first transistor is coupled to the first current-carrying terminal of the second transistor and the control terminal of the second transistor is coupled to a low impedance alternating current (AC) node; a bias network that includes a first circuit element and a second circuit element, wherein the first circuit element couples the second current-carrying terminal of the second transistor to the control terminal of the second transistor with a direct current (DC) coupling, wherein the first circuit element is configured to apply a portion of a potential at the second current-carrying terminal of the second transistor to the control terminal of the second transistor, and wherein the second circuit element is coupled between the control terminal of the second transistor and a fixed potential; and a feedback network that directly connects the control terminal of the first transistor to the second current-carrying terminal of the first transistor and the first current-carrying terminal of the second transistor. 2. The amplifier of claim 1 , wherein the first transistor and the second transistor are configured as field effect transistors, and wherein the first current-carrying terminals are configured as source terminals, the second current-carrying terminals are configured as drain terminals, and the control terminals are configured as gate terminals. 3. The amplifier of claim 1 , wherein the feedback network includes a resistor and a capacitor connected in series to the resistor. 4. The amplifier of claim 1 , wherein the low impedance AC node is coupled to a first terminal of a capacitor, and wherein a second terminal of the capacitor is coupled to a fixed potential. 5. The amplifier of claim 1 , wherein the first circuit element includes a first bias resistor, and the second circuit element includes a second bias resistor. 6. An amplifier comprising: a first transistor that includes a first current-carrying terminal, a second current-carrying terminal, and a control terminal; a second transistor that includes a first current-carrying terminal, a second current-carrying terminal, and a control terminal, wherein the second current-carrying terminal of the first transistor is coupled to the first current-carrying terminal of the second transistor and the control terminal of the second transistor is coupled to a low impedance alternating current (AC) node; a bias network that includes a first circuit element and a second circuit element, wherein the first circuit element couples the second current-carrying terminal of the second transistor to the control terminal of the second transistor, wherein the first circuit element is configured to apply a portion of a potential at the second current-carrying terminal of the second transistor to the control terminal of the second transistor, and wherein the second circuit element is coupled between the control terminal of the second transistor and a fixed potential; wherein the first circuit element includes a first bias resistor, and the second circuit element includes a second bias resistor; and wherein, during operation, the first bias resistor and the second bias resistor create a first bias voltage between the second current-carrying terminal of the first transistor and the first current-carrying terminal of the first transistor, and create a second bias voltage between the second current-carrying terminal of the second transistor and the first current-carrying terminal of the second transistor, and wherein during operation, the first bias voltage and the second bias voltage are equal. 7. An amplifier comprising: a first transistor that includes a first current-carrying terminal, a second current-carrying terminal, and a control terminal; a second transistor that includes a first current-carrying terminal, a second current-carrying terminal, and a control terminal, wherein the second current-carrying terminal of the first transistor is coupled to the first current-carrying terminal of the second transistor and the control terminal of the second transistor is coupled to a low impedance alternating current (AC) node; a bias network that includes a first circuit element and a second circuit element, wherein the first circuit element couples the second current-carrying terminal of the second transistor to the control terminal of the second transistor, wherein the first circuit element is configured to apply a portion of a potential at the second current-carrying terminal of the second transistor to the control terminal of the second transistor, and wherein the second circuit element is coupled between the control terminal of the second transistor and a fixed potential; wherein the first circuit element includes a first bias resistor, and the second circuit element includes a second bias resistor; and wherein, during operation, the first bias resistor and the second bias resistor create a first bias voltage between the second current-carrying terminal of the first transistor and the first current-carrying terminal of the second transistor, and create a second bias voltage between the second current-carrying terminal of the second transistor and the first current-carrying terminal of the second transistor, and wherein during operation, the first bias voltage and the second bias voltage are un-equal. 8. The amplifier of claim 5 , wherein the first bias resistor and the second bias resistor are selected such that, during operation, the first transistor and the second transistor are biased in a forward-active mode of operation. 9. The amplifier of claim 1 further comprising one or more additional transistors, wherein each of the one or more additional transistors includes a first current-carrying terminal, a second current-carrying terminal, and a control terminal, and wherein each of the one or more additional transistors are cascode-coupled to the second transistor or to another one of the additional transistors. 10. An amplifier comprising: a first transistor that includes a first current-carrying terminal, a second current-carrying terminal, and a control terminal; a second transistor that includes a first current-carrying terminal, a second current-carrying terminal, and a control terminal, wherein the second current-carrying terminal of the first transistor is coupled to the first current-carrying terminal of the second transistor and the control terminal of the second transistor is coupled to a low impedance alternating current (AC) node; a bias network that includes a first circuit element and a second circuit element, wherein the first circuit element couples the second current-carrying terminal of the second transistor to the control terminal of the second transistor, wherein the first circuit element is configured to apply a portion of a potential at the second current-carrying terminal of the second transistor to the control terminal of the second transistor, and wherein the second circuit element is coupled between the control terminal of the second transistor and a fixed potential; and wherein the amplifier comprises a plurality of cells including at least a first cell and a second cell, wherein the first transistor and the second transistor are included in a portion of the first cell, wherein a third transistor and a fourth transistor are included in a portion of the second cell, wherein the control terminal of the first

Assignees

Inventors

Classifications

  • H03F1/0205Primary

    in transistor amplifiers · CPC title

  • H03F3/195Primary

    in integrated circuits · CPC title

  • the amplifier being a radio frequency amplifier · CPC title

  • Feedback used to stabilise the amplifier · CPC title

  • the cascode amplifier has more than one common gate stage · CPC title

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What does patent US10608588B2 cover?
Embodiments of an amplifiers and integrated circuits include a first transistor and a second transistor. A second current-carrying terminal of the first transistor may be coupled to a first current-carrying terminal of the second transistor and the control terminal of the second transistor may be coupled to a low impedance alternating current (AC) potential node. A bias network that includes a …
Who is the assignee on this patent?
Nxp Usa Inc
What technology area does this patent fall under?
Primary CPC classification H03F1/0205. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).