Internal voltage generation circuit

US10608529B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10608529-B2
Application numberUS-201916283037-A
CountryUS
Kind codeB2
Filing dateFeb 22, 2019
Priority dateFeb 28, 2018
Publication dateMar 31, 2020
Grant dateMar 31, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An internal voltage veneration circuit includes negative voltage generation circuits of a first type and a second type, and the negative voltage generation circuits of the first type and the second type are connected parallel to each other. A drive signal is input to a charge pump circuit from a signal drive circuit in opposite phases in the negative voltage generation circuits of the first type and in the negative voltage generation circuits of the second type. A plurality of pairs of a negative voltage generation circuit of the first type and a negative voltage generation circuit of the second type are disposed, and the negative voltage generation circuit of the first type and the negative voltage generation circuit of the second type are located adjacent to each other.

First claim

Opening claim text (preview).

What is claimed is: 1. An internal voltage generation circuit formed on a semiconductor integrated circuit, the internal voltage generation circuit comprising: an oscillator circuit that generates an oscillator signal; a first voltage generation unit and a second voltage generation unit, each of which includes a charge pump circuit and a signal drive circuit that receives the oscillator signal and that generates one or more drive signals to drive the charge pump circuit; and an output control circuit that controls an output voltage that is output from the charge pump circuit, wherein the first voltage generation unit and the second voltage generation unit are connected parallel to each other, the one or more drive signals are input in opposite phases to the charge pump circuit in the first voltage generation unit and to the charge pump circuit in the second voltage generation unit, a plurality of pairs of the first voltage generation unit and the second voltage generation unit are disposed, the first voltage generation unit and the second voltage generation unit are located adjacent to each other, and the first voltage generation unit and the second voltage generation unit that are located adjacent to each other in a freely selected combination are configured to be simultaneously switched on and off. 2. The internal voltage generation circuit according to claim 1 , wherein a plurality of first voltage generation units and a plurality of second voltage generation units are arranged in a plurality of columns that are connected parallel to each other, the plurality of first voltage generation units and the plurality of second voltage generation units are alternately arranged in a column direction and in a row direction, and the combination of the first voltage generation unit and the second voltage generation unit that are simultaneously switched on and off includes the first voltage generation unit and the second voltage generation unit that are arranged in the row direction. 3. The internal voltage generation circuit according to claim 1 , wherein the freely selected combination is constituted by units selected from the first voltage generation units and the second voltage generation units excluding at least the first voltage generation unit or the second voltage generation unit located at one end of the arrangement of the first voltage generation units and the second voltage generation units. 4. An internal voltage generation circuit formed on a semiconductor integrated circuit, the internal voltage generation circuit comprising: an oscillator circuit that generates an oscillator signal; a first voltage generation unit and a second voltage generation unit, each of which includes a charge pump circuit and a signal drive circuit that receives the oscillator signal and that generates one or more drive signals to drive the charge pump circuit; and an output control circuit that controls an output voltage that is output from the charge pump circuit, wherein the first voltage generation unit and the second voltage generation unit are connected parallel to each other, the one or more drive signals are input in opposite phases to the charge pump circuit in the first voltage generation unit and to the charge pump circuit in the second voltage generation unit, a plurality of pairs of the first voltage generation unit and the second voltage generation unit are disposed, the first voltage generation unit and the second voltage generation unit are located adjacent to each other, the oscillator circuit generates oscillator signals having different phases, and the signal drive circuit receives the oscillator signals and generates the one or more drive signals at regular phase intervals.

Assignees

Inventors

Classifications

  • H02M3/07Primary

    using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

  • Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Circuitry for control of the power supply · CPC title

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What does patent US10608529B2 cover?
An internal voltage veneration circuit includes negative voltage generation circuits of a first type and a second type, and the negative voltage generation circuits of the first type and the second type are connected parallel to each other. A drive signal is input to a charge pump circuit from a signal drive circuit in opposite phases in the negative voltage generation circuits of the first typ…
Who is the assignee on this patent?
Sharp Kk
What technology area does this patent fall under?
Primary CPC classification H02M3/07. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).