Self-gated RRAM cell and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10608177-B2
Application number	US-201415525200-A
Country	US
Kind code	B2
Filing date	Dec 26, 2014
Priority date	Dec 26, 2014
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

The present disclosure discloses a self-gated RRAM cell and a manufacturing method thereof; which belong to the field of microelectronic technology. The self-gated RRAM cell comprises: a stacked structure containing multiple layers of conductive lower electrodes; a vertical trench formed by etching the stacked structure; a M8XY6 gated layer formed on an inner wall and a bottom of the vertical trench; a resistance transition layer formed on a surface of the M8XY6, gated layer; and a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode. The present disclosure is implemented on a basis of using the self-gated RRAM as a memory cell. It may not depend on a gated transistor and a diode, but relies on a non-linear variation characteristic of resistance of its own varied with voltage to achieve a self-gated function, which has a simple structure, easy integration, high density and low cost, capable of suppressing a reading crosstalk phenomenon in a cross array structure; and is also adapted for a planar stacked cross array structure and a vertical cross array structure, achieving 3D storage with a high density.

First claim

We claim:

1. A self-gated Resistive Random Access Memory (RRAM) cell, comprising:
a substrate;
a stacked structure on the substrate containing multiple layers of conductive lower electrodes, a first insulating dielectric layer, a second insulating dielectric layer, and a third insulating dielectric layer, wherein the first insulating dielectric layer is directly on the substrate;
a vertical trench formed through the stacked structure, wherein a bottom of the vertical trench is formed within the first insulating dielectric layer;
a M 8 XY 6 gated layer formed on an inner wall and a bottom of the vertical trench, whose resistance shows a highly non-linear characteristic varied with voltage, wherein the M 8 XY 6 gated layer is isolated from the substrate by the first insulating dielectric layer;
a resistance transition layer formed on a surface of the M 8 XY 6 gated layer, wherein the M 8 XY 6 gated layer and the resistance transition layer are directly adjacent to each other without a conductive layer therebetween; and
a conductive upper electrode formed on a surface of the resistance transition layer, the vertical trench being filled with the conductive upper electrode.

2. The self-gated RRAMV cell according to claim 1 , wherein in the stacked structure containing the multiple layers of conductive lower electrodes, the multiple layers of conductive lower electrodes are used as word lines in a vertical cross array structure, any two layers of the multiple layers of conductive lower electrodes being isolated by the second insulating dielectric layer, a top layer of the multiple layers of conductive lower electrodes being covered by the third insulating dielectric layer, and a bottom layer of the multiple layers of conductive lower electrodes being isolated from the substrate by the first insulating dielectric layer.

3. The self-gated RRAM cell according to claim 2 , wherein
the conductive lower electrodes are made of any of conductive materials selected from a group constituted of metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO 2 , CuTe, Cu 3 Ge, ITO or IZO, or are made of alloy of any two or more conductive materials selected from a group constituted of metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO 2 , CuTe, Cu 3 Ge, ITO or IZO; and
the conductive lower electrodes are formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

4. The self-gated RRAMV cell according to claim 2 , wherein the first insulating dielectric layer is made of SiN, SiO, SiON, SiO 2 doped with C, SiO 2 doped with P or SiO 2 doped with F; and
the first insulating dielectric layer is formed with a thickness of 10 nm-100 nm by chemical vapor deposition or sputtering.

5. The self-gated RRAMV cell according to claim 2 , wherein the stacked structure is constituted by two layers of the multiple layers of conductive lower electrodes which are a first conductive lower electrode and a second conductive lower electrode, the second conductive lower electrode being formed on the first conductive lower electrode, and the first conductive lower electrode being isolated from the second conductive lower electrode by the second insulating dielectric layer, the second conductive lower electrode being covered by the third insulating dielectric layer, and the first conductive lower electrode being isolated from the substrate by the first insulating dielectric layer.

6. The self-gated RRAMV cell according to claim 2 , wherein the vertical trench goes through the third insulating dielectric layer covering the multiple layers of conductive lower electrodes, the multiple layers of conductive lower electrodes and the first second and third insulating dielectric layers sandwiched between the multiple layers of conductive lower electrodes sequentially, and the bottom of the vertical trench is formed within the first insulating dielectric layer under the bottom layer of the multiple layers of conductive lower electrodes.

7. The self-gated RRAM cell according to claim 1 , wherein
for the M 8 XY 6 gated layer formed on the inner wall and the bottom of the vertical trench, M is any of Cu, Ag, Li, Ni or Zn, X is any of Ge, Si, Sn, C or N, and Y is any of Se, S, O or Te.

8. The self-gated RRAM cell according to claim 7 , wherein
the M 8 XY 6 gated layer formed on the inner wall and the bottom of the vertical trench is further made of doped M 8 XY 6 material, doping element(s) being one or more of N, P, Zn, Cu, Ag, Li, Ni, Zn, Ge, Si, Sn, C, N, Se, S, O, Te, Br, Cl, F or I.

9. The self-gated RRAM cell according to claim 1 , wherein
the M 8 XY 6 gated layer formed on the inner wall and the bottom of the vertical trench is formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

10. The self-gated RRAM cell according to claim 1 , wherein
the resistance transition layer formed on the surface of the M 8 XY 6 gated layer is made of any of inorganic material CuS, AgS, AgGeSe, CuI x S y , ZrO 2 , HfO 2 , TiO 2 , SiO 2 , WO x , NiO, CuO x , ZnO, TaO x , CoO, Y 2 O 3 , Si, PCMO, SZO or STO, or is made of any of organic material TCNQ, PEDOT, P 3 HT or PCTBT, or is made of a material formed by the inorganic material or the organic material being doped and characteristic modified; and
the resistance transition layer is formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, spin coating, or deposition by magnetron sputtering.

11. The self-gated RLRAMIV cell according to claim 1 , wherein the conductive upper electrode formed within the vertical trench whose inner wall is covered by the M 8 XY 6 gated layer and the resistance transition layer, and an upper surface of the conductive upper electrode is flushed with an upper surface of the third insulating dielectric layer covering a top layer of the multiple layers of conductive lower electrodes.

12. The self-gated RRAM cell according to claim 11 , wherein
the conductive upper electrode is made of any of conductive materials selected from metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO 2 , CuTe, Cu 3 Ge, ITO or IZO, or is alloy made of any two or more conductive materials selected from metal material W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir or Ni and metal compound TiN, TaN, IrO 2 , CuTe, Cu 3 Ge, ITO or IZO; and
the conductive upper electrode is formed with a thickness of 1 nm-500 nm by electron beam evaporation, chemical vapor deposition, pulse laser deposition, atomic layer deposition, or deposition by magnetron sputtering.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Lv Hangbing
• Liu Ming
• Liu Qi
• Long Shibing

Classifications

• H01L45/144

  Electricity · mapped topic

• H01L27/249

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic

• H01L45/14

  Electricity · mapped topic

• H01L45/1253 Primary

  Electricity · mapped topic