Array substrate, its manufacturing method, and a display device

Patent metadata

Field	Value
Publication number	US-10608019-B2
Application number	US-201816107884-A
Country	US
Kind code	B2
Filing date	Aug 21, 2018
Priority date	Oct 27, 2017
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A method for manufacturing an array substrate, including forming at least two data lines, forming a buffer layer on the data lines, forming an organic film, which is provided with vias, on the buffer layer, the vias being in a partially overlapping relationship with the orthographic projection of the two adjacent data lines on a base substrate, forming a first conductive layer on the organic film.

First claim

What is claimed is:

1. A method for manufacturing an array substrate, comprising:
forming at least two data lines;
forming a buffer layer on the at least two data lines;
forming an organic film, which is provided with vias, on the buffer layer, wherein the vias are in a partially overlapping relationship with an orthographic projection of two adjacent data lines of the at least two data lines on a base substrate; and
forming a first conductive layer on the organic film.

2. The method according to claim 1 , wherein forming the at least two data lines comprises:
forming extension regions facing each other, the extension regions are respectively formed in the two adjacent data lines; wherein the vias are in an overlapping relationship with the orthographic projection of the extension regions on the base substrate.

3. The method according to claim 1 , wherein before the at least two data lines are formed, a gate layer is formed on the base substrate, and a gate insulating layer is formed on the gate layer, and an active layer is formed on the gate insulating layer.

4. The method according to claim 3 , further comprising:
forming a source drain electrode on the active layer at the same time that the at least two data lines are formed on the active layer, and the buffer layer is formed on the at least two data lines, the source drain electrode and the active layer.

5. The method according to claim 1 , wherein after the first conductive layer is formed on the organic film, a passivation layer is formed on the first conductive layer; and a second conductive layer is formed on the passivation layer.

6. The method according to claim 1 , wherein the at least two data lines and the vias, which are formed in the organic film, are arranged in a dummy pixel region.

7. The method according to claim 2 , wherein the at least two data lines and the vias, which are formed in the organic film, are arranged in a dummy pixel region.

8. The method according to claim 4 , wherein the at least two data lines and the vias, which are formed in the organic film, are arranged in a dummy pixel region.

9. The method according to claim 5 , wherein the at least two data lines and the vias, which are formed in the organic film, are arranged in a dummy pixel region.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Cao Binbin
• Zhang Hui
• Ai Li

Classifications

• G02F1/1333 Primary

  Constructional arrangements; {Manufacturing methods}(G02F1/135, G02F1/136 take precedence) · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G02F1/1362 Primary

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• H01L27/124 Primary

  Electricity · mapped topic

• H01L27/3258

  Electricity · mapped topic