Battery management chip circuit on the base of silicon on insulator (SOI) process

Patent metadata

Field	Value
Publication number	US-10608014-B2
Application number	US-201616085423-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Mar 16, 2016
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A battery management chip circuit on the basis of an SOI process. The battery management chip circuit comprises a high-voltage multiplexer MUX, a voltage reference circuit, a Sigma-delta ADC (comprising an analog modulator and a digital filter), an SPI communication circuit, a function control circuit and a voltage value register. The battery management chip circuit is integrated on the basis of an SOI high-voltage process, and particularly, high-voltage MOS transistors adopted by the battery management chip circuit are high-voltage MOS device units on the basis of the SOI process. In addition, the present invention highlights the design of interface circuit-chopper circuit of the high-voltage multiplexer MUX and the Sigma-delta ADC, so as to describe the advantages such as decrease of difficulty of circuit design and reduction of layout area brought about when the present invention adopts the SOI process design and tape-out.

First claim

What is claimed is:

1. A battery management chip circuit on a basis of a SOI process comprising:
the battery management chip circuit is integrated on a basis of a SOI high-voltage process and comprises an input interface circuit for an analog modulator;
the input interface circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first diode, a second diode, a first capacitor and a second capacitor integrated on the basis of the SOI process, wherein source ends of the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are connected with positive electrodes of the first diode and the second diode and are connected with an input voltage, a gate electrode of the first MOS transistor, a gate electrode of the fourth MOS transistor and a drain electrode of the third MOS transistor are connected with a negative electrode of the first diode and a negative electrode of the first capacitor, and gate electrodes of the second MOS transistor and the third MOS transistor and a drain electrode of the fourth MOS transistor are connected with a negative electrode of the second diode and a negative electrode of the second capacitor, and positive electrodes of the first capacitor and the second capacitor are respectively connected with non-overlapping complementary clock signals; and drain electrodes of the first MOS transistor and the second MOS transistor are respectively used as output ends of the circuit.

2. The battery management chip circuit on the basis of the SOI process according to claim 1 , wherein high-voltage MOS transistors adopted by the battery management chip circuit are high-voltage MOS device units on the basis of the SOI process.

3. The battery management chip circuit on the basis of the SOI process according to claim 2 , wherein the MOS device unit on the basis of the SOI process comprises:
a SOI substrate, comprising a silicon substrate, an insulating layer and a top layer silicon, a NMOS device or/and a PMOS device is formed in the top layer silicon;
the NMOS device is formed in a P-well region of the top layer silicon and comprises a N+ type source region, a N+ type drain region, a gate electrode structure and a P+ type body region, the P+ type body region and the N+ type source region are isolated by adopting a shallow channel structure;
the PMOS device is formed in a N-well region of the top layer silicon and comprises a P+ type source region, a P+ type drain region, a gate electrode structure and a N+ type body region, the N+ type body region and the P+ type source region are isolated by adopting a shallow channel structure.

4. The battery management chip circuit on the basis of the SOI process according to claim 3 , wherein the MOS device unit on the basis of the SOI process comprises the NMOS device and the PMOS device, and the NMOS device and the PMOS device are isolated by adopting the shallow channel structure.

5. The battery management chip circuit on the basis of the SOI process according to claim 3 , wherein the NMOS device comprises four leading-out ends respectively corresponding to the N+ type source region, the N+ type drain region, the gate electrode structure and the P+ type body region.

6. The battery management chip circuit on the basis of the SOI process according to claim 3 , wherein the PMOS device comprises four leading-out ends respectively corresponding to the P+ type source region, the P+ type drain region, the gate electrode structure and the N+ type body region.

7. The battery management chip circuit on the basis of the SOI process according to claim 2 , wherein the MOS device units on the basis of the SOI process are isolated by adopting a deep trench structure, and the deep trench structure comprises a deep trench at least penetrating through the top layer silicon and an insulating material filled in the deep trench.

8. The battery management chip circuit on the basis of the SOI process according to claim 1 , wherein a working voltage of the battery management chip circuit is 0-60V.

Assignees

• Shanghai Inst Microsystem & Information Tech Cas

Inventors

• Cheng Xinhong
• Li Xinchang
• Wu Zhonghao
• Xu Dawei
• Yu Yuehui

Classifications

• H03K17/567

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

• H01M10/425

  Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing (printed circuits H05K1/00) · CPC title

• H01M2010/4271

  Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing · CPC title

• H01M10/42 Primary

  Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells (H01M10/60 takes precedence) · CPC title

• H01M10/4264

  with capacitors · CPC title