Integrated capacitor filter and integrated capacitor filter with varistor function

US10607777B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10607777-B2
Application numberUS-201815887108-A
CountryUS
Kind codeB2
Filing dateFeb 2, 2018
Priority dateFeb 6, 2017
Publication dateMar 31, 2020
Grant dateMar 31, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed are apparatus and a method for providing an integrated multiterminal multilayer ceramic device that has three or more capacitive elements. Two of such capacitive elements may be in series, with a third in parallel. The integrated device may be packaged as an overmolded three leaded component, or can be mounted as SMD (surface mount device). The integrated device may also be combined with a separate varistor in a stacked arrangement of leaded components.

First claim

Opening claim text (preview).

What is claimed is: 1. A multiterminal multilayer ceramic device with multiple capacitive elements, comprising: a body having cooperating multiple layers including electrode layers to form integrated capacitive structures; a first region of said electrode layers forming a split feedthrough type construction of two respective capacitors; a second region of said electrode layers forming an overlap type construction of a multilayer ceramic capacitor; a first pair of terminations external to said body and having opposite polarity; and a second pair of terminations external to said body and having the same polarity; wherein said first pair of terminations is in series connection with said second region capacitor, and said first pair of terminations and at least one of said second pair of terminations are in respective parallel connections with said two respective capacitors of said first region, so that multiple capacitive elements are integrated in a single package device. 2. A multiterminal multilayer ceramic device as in claim 1 , wherein said first region of said electrode layers comprises at least a pair of layers situated opposite a generally cross-shaped layer having respective front and back extending edges in respective contact with said second pair of terminations, and having side extending edges in respective contact with said first pair of terminations. 3. A multiterminal multilayer ceramic device as in claim 2 , wherein said pair of layers of said first layer have respectively different overlap areas with said generally cross-shaped layer of said first layer so that different capacitance values result for said respective capacitors of said first region. 4. A multiterminal multilayer ceramic device as in claim 3 , further comprising: a third region of said electrode layers forming a split feedthrough type construction of an additional two respective capacitors, said third region comprising at least a pair of layers having respective front and back extending edges in respective contact with said second pair of terminations, and having side extending edges in respective contact with said first pair of terminations; wherein said pair of layers of said third layer have respectively different overlap areas with said generally cross-shaped layer of said third layer so that different capacitance values result for said respective additional capacitors of said third region. 5. A multiterminal multilayer ceramic device as in claim 2 , wherein the pair of layers of the first region are T-shaped. 6. A multiterminal multilayer ceramic device as in claim 2 , wherein the body has a pair of opposing side surfaces and the second pair of terminations are respectively formed on the pair of opposing side surfaces, and wherein the pair of layers of the first region respectively connect with the first pair of terminations along the pair of opposing side surfaces of the body. 7. A multiterminal multilayer ceramic device as in claim 1 , wherein said second region of said electrode layers comprises at least paired alternating layers in an overlapped configuration with respective extending portions thereof in contact with respective of said first pair of terminations. 8. A multiterminal multilayer ceramic device as in claim 7 , wherein the paired alternating layers of the second region are T-shaped. 9. A multiterminal multilayer ceramic device as in claim 7 , wherein the body has a pair of opposing side surfaces and the second pair of terminations are respectively formed on the pair of opposing side surfaces, and wherein the paired alternating layers of the second region respectively extend to the pair of opposing side surfaces of the body, and wherein the paired alternating layers of the second region respectively connect with the first pair of terminations along the pair of opposing side surfaces of the body. 10. A multiterminal multilayer ceramic device as in claim 1 , wherein said two respective capacitors of said first region are in series with each other, and both in parallel with said multilayer ceramic capacitor of said second region. 11. A multiterminal multilayer ceramic device as in claim 1 , wherein said first and second pairs of terminations are situated on respective opposing-side pairs of sides of said body, and respectively wrap-around therefrom to a designated bottom side of said body, for forming a surface mount device (SMD) configuration for said device. 12. A multiterminal multilayer ceramic device as in claim 1 , further including first and second leads respectively attached to said first pair of terminations, and a third lead attached to at least one of said second pair of terminations. 13. A multiterminal multilayer ceramic device as in claim 12 , wherein a discrete varistor with a pair of external terminations is stacked relative to said device, with said first and second leads respectively attached to said pair of external terminations of said varistor so that said device and said discrete varistor are connected in parallel. 14. A multiterminal multilayer ceramic device as in claim 1 , further comprising: a third region of said electrode layers forming a split feedthrough type construction of an additional two respective capacitors; wherein said first pair of terminations and at least one of said second pair of terminations are in respective parallel connections with said additional two respective capacitors of said third region. 15. A multiterminal multilayer ceramic device as in claim 1 , wherein said second region of said electrode layers is between said first and third regions of said electrode layers. 16. A multiterminal multilayer ceramic device as in claim 1 , wherein: said body has a pair of relatively elongated sides and a pair of relatively shorter sides; said first pair of terminations reside respectively on said pair of relatively elongated sides; and said second pair of terminations resides respectively on said pair of relatively shorter sides. 17. A multiterminal multilayer ceramic device as in claim 1 , wherein said electrode layers of said second region include relatively enlarged areas for forming a relatively increased capacitance value overlap type multilayer ceramic capacitor.

Assignees

Inventors

Classifications

  • voltage responsive, i.e. varistors · CPC title

  • H01G4/228Primary

    Terminals · CPC title

  • Multiple capacitors, i.e. structural combinations of fixed capacitors · CPC title

  • containing also titanates · CPC title

  • based on niobium or tungsteen, tantalum oxides or niobates, tantalates · CPC title

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What does patent US10607777B2 cover?
Disclosed are apparatus and a method for providing an integrated multiterminal multilayer ceramic device that has three or more capacitive elements. Two of such capacitive elements may be in series, with a third in parallel. The integrated device may be packaged as an overmolded three leaded component, or can be mounted as SMD (surface mount device). The integrated device may also be combined w…
Who is the assignee on this patent?
Avx Corp
What technology area does this patent fall under?
Primary CPC classification H01G4/228. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).