Memory components and controllers that calibrate multiphase synchronous timing references

Patent metadata

Field	Value
Publication number	US-10607670-B2
Application number	US-201715794177-A
Country	US
Kind code	B2
Filing date	Oct 26, 2017
Priority date	Apr 22, 2011
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

First claim

What is claimed is:

1. A memory device, comprising:
a first register to store a first configuration value associated with a first one of a plurality of bitslices, the plurality of bitslices to send and receive data, the data to be stored and retrieved by the memory device; and,
a second register to store a second configuration value associated with a second one of the plurality of bitslices, the first configuration value to be addressed to the first register by being received by the first one of the plurality of bitslices and the second configuration value to be addressed to the second register by being received by the second one of the plurality of bitslices.

2. The memory device of claim 1 , wherein a first timing adjustment is determined by the first configuration value.

3. The memory device of claim 2 , wherein a second timing adjustment is determined by the second configuration value.

4. The memory device of claim 3 , wherein the first timing adjustment to affect a first internal timing of the first bitslice, the second timing adjustment to affect a second internal timing of the second bitslice, the second configuration value not to affect the first internal timing of the first bitslice, the first configuration value not to affect the second internal timing.

5. The memory device of claim 4 , wherein the first internal timing and the second internal timing affect a same timing parameter of the first bitslice and the second bitslice, respectively.

6. The memory device of claim 5 , wherein the same timing parameter is associated with a quadrature clock duty cycle.

7. The memory device of claim 5 , wherein the same timing parameter is associated with a quadrature phase offset of a quadrature clock.

8. A memory controller, comprising:
a first circuit to send, to a memory device, a first configuration value associated with a first one of a plurality of bitslices of the memory device, the plurality of bitslices to send and receive data, the data to be stored and retrieved by the memory device; and,
a second circuit to send, to the memory device, a second configuration value associated with a second one of the plurality of bitslices of the memory device, the first configuration value to be addressed to the first register by being sent to at least the first one of the plurality of bitslices and the second configuration value to be addressed to the second register by being sent to at least the second one of the plurality of bitslices.

9. The memory controller of claim 8 , wherein a first timing adjustment internal to the memory device is determined by the first configuration value.

10. The memory controller of claim 9 , wherein a second timing adjustment internal to the memory device is determined by the second configuration value.

11. The memory controller of claim 10 , wherein the first timing adjustment is to affect a first internal timing of the first bitslice, the second timing adjustment to affect a second internal timing of the second bitslice, the second configuration value not to affect the first internal timing of the first bitslice, the first configuration value not to affect the second internal timing.

12. The memory controller of claim 11 , wherein the first internal timing and the second internal timing affect a same timing parameter of the first bitslice and the second bitslice, respectively.

13. The memory controller of claim 5 , wherein the same timing parameter is associated with at least one of a quadrature clock duty cycle and a quadrature phase offset of a quadrature clock.

Assignees

• Rambus Inc

Inventors

• Giovannini Thomas
• Best Scott
• Luo Lei
• Shaeffer Ian

Classifications

• G11C7/227

  Timing of memory operations based on dummy memory elements or replica circuits · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C29/50012

  of timing · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title