Data output circuit

Patent metadata

Field	Value
Publication number	US-10607667-B2
Application number	US-201916248416-A
Country	US
Kind code	B2
Filing date	Jan 15, 2019
Priority date	Jun 1, 2018
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A data output circuit includes: a voltage generation circuit configured to generate an operating voltage having a potential level higher than levels of a first power supply voltage and a second power supply voltage; a pre-driver circuit configured to generate pull-up code signals and pull-down code signals according to calibration code signals and the operating voltage; a data pre-driver circuit configured to generate and output internal data according to a data signal and the first power supply voltage; and a main driver circuit configured to generate output data according to the internal data and the second power supply voltage, wherein a driving strength of the main driver circuit is adjusted according to the pull-up code signals and the pull-down code signals.

First claim

What is claimed is:

1. A data output circuit comprising:
a voltage generation circuit configured to generate an operating voltage having a potential level higher than levels of a first power supply voltage and a second power supply voltage;
a pre-driver circuit configured to generate pull-up code signals and pull-down code signals according to calibration code signals and the operating voltage;
a data pre-driver circuit configured to generate and output internal data according to a data signal and the first power supply voltage; and
a main driver circuit configured to generate output data according to the internal data and the second power supply voltage, wherein a driving strength of the main driver circuit is adjusted according to the pull-up code signals and the pull-down code signals.

2. The data output circuit of claim 1 , wherein the voltage generation circuit includes:
a charge pump configured to generate a high voltage by performing a pumping operation in response to the first power supply voltage, a clock signal, and an enable control signal;
a replica circuit configured to generate a replica voltage having a potential level corresponding to a first logic level of the output data output from the main driver circuit; and
a regulator configured to generate the enable control signal for controlling the pumping operation of the charge pump in response to the replica voltage and a reference voltage, and output the operating voltage by adjusting a potential level of a high voltage.

3. The data output circuit of claim 1 , further comprising a ZQ calibration code generation circuit configured to generate the calibration code signals,
wherein the ZQ calibration code generation circuit generates the calibration code signals according to a first calibration code value corresponding to a change in temperature and a second calibration code value corresponding to a change in power supply voltage.

4. The data output circuit of claim 3 , wherein the ZQ calibration code generation circuit skips an operation of detecting the change in power supply voltage and calibrating the detected change, and uses the second calibration code value fixed to a certain value.

5. The data output circuit of claim 1 , wherein the pre-driver circuit includes:
a pull-up pre-driver configured to generate the pull-up code signals according to the calibration code signals; and
a pull-down pre-driver configured to generate the pull-down code signals according to the calibration code signals,
wherein the pull-up pre-driver and the pull-down pre-driver increase levels of signals having a logic high level among the pull-up code signals and the pull-down code signals to the level of the operating voltage, using the operating voltage, and outputs the signals.

6. The data output circuit of claim 1 , wherein the main driver circuit includes a pull-up circuit, a trimming circuit, and a pull-down circuit, which are coupled in series between a terminal to which the second power supply voltage is applied and a terminal to which a ground voltage is applied,
wherein the pull-up circuit applies the second power supply voltage to the trimming circuit in response to the internal data, and
wherein the pull-down circuit applies the ground voltage to the trimming circuit in response to the internal data.

7. The data output circuit of claim 6 , wherein the pull-up circuit includes a PMOS transistor, and the pull-down circuit includes an NMOS transistor.

8. The data output circuit of claim 6 , wherein the trimming circuit includes a plurality of trimming units commonly coupled to an output node,
wherein each of the plurality of trimming units is activated or inactivated in response to one of the pull-up or pull-down code signals.

9. The data output circuit of claim 8 , wherein each of the plurality of trimming units includes:
a first NMOS transistor coupled between the pull-up circuit and the output node to be turned on or turned off in response to one of the pull-up code signals; and
a second NMOS transistor coupled between the output node and the pull-down circuit to be turned on or turned off in response to one of the pull-down code signals.

10. A data output circuit comprising:
a voltage generation circuit configured to generate an operating voltage having a level higher than that of a power supply voltage;
a pre-driver circuit configured to generate pull-up code signals and pull-down code signals according to the operating voltage, wherein the pull-up code signals and the pull-down code signals are generated to have a level of a ground voltage or a level of the operating voltage; and
a main driver circuit configured to generate output data corresponding to the level of the power supply voltage or the level of the ground voltage according to internal data, wherein a driving strength of the main driver circuit is adjusted according to the pull-up code signals and the pull-down code signals.

11. The data output circuit of claim 10 , wherein the voltage generation circuit includes:
a charge pump configured to generate a high voltage by performing a pumping operation in response to the power supply voltage, a clock signal, and an enable control signal;
a replica circuit configured to generate a replica voltage having a potential level substantially the same as the level of the power supply voltage of the output data output from the main driver circuit; and
a regulator configured to generate the enable control signal for controlling the pumping operation of the charge pump in response to the replica voltage and a reference voltage, and output the operating voltage by adjusting a potential level of a high voltage.

12. The data output circuit of claim 10 , wherein the main driver circuit includes a pull-up circuit, a trimming circuit, and a pull-down circuit, which are coupled in series between a first terminal to which the power supply voltage is applied and a second terminal to which the ground voltage is applied.

13. The data output circuit of claim 12 , wherein the trimming circuit includes a plurality of trimming units commonly coupled to an output node,
wherein each of the plurality of trimming units is activated or inactivated in response to one of the pull-up or pull-down code signals.

14. The data output circuit of claim 13 , wherein each of the plurality of trimming units includes:
a first NMOS transistor coupled between the pull-up circuit and the output node to be turned on or turned off in response to one of the pull-up code signals; and
a second NMOS transistor coupled between the output node and the pull-down circuit to be turned on or turned off in response to one of the pull-down code signals.

15. The data output circuit of claim 12 , wherein the pull-up circuit includes a PMOS transistor coupled between the first terminal and the trimming circuit, the PMOS transistor being turned on or turned off in response to the internal data.

16. The data output circuit of claim 12 , wherein the pull-down circuit includes an NMOS transistor coupled between the trimming circuit and the second terminal, the NMOS transistor being turned on or turned off in response to the internal data.

17. A data output circuit comprising:
a voltage generation circuit operably coupled to a first power supply voltage and configured to generate an operating voltage having a level higher than a level of the first power supply voltage;
a calibration code generation circuit configured to generate calibration code signals based on a temperature change and a fixed power supply voltage;
a pre-driver circuit configured to

Assignees

• Sk Hynix Inc

Inventors

• Kim Hee Jun
• Hwang Minsoon

Classifications

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C7/1051 Primary

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C5/145

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title

• G11C29/022

  in I/O circuitry · CPC title