Display device and method of driving the same

Patent metadata

Field	Value
Publication number	US-10607563-B2
Application number	US-201715432359-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Aug 23, 2016
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A display device includes a timing controller, a driver, and a display panel. The timing controller outputs a first clock signal having first rising time during an active section and a second clock signal having second rising time during a blank section adjacent to the active section. The driver generates a data signal based on the first clock signal and the second clock signal and to output the data signal. The display panel displays an image based on the data signal. The first rising time is shorter than the second rising time.

First claim

What is claimed is:

1. A display device, comprising:
a timing controller to output a first clock signal having first rising time during an active section and a second clock signal having second rising time during a blank section adjacent to the active section;
a driver to generate a data signal based on the first clock signal and the second clock signal and to output the data signal; and
a display panel to display an image based on the data signal, wherein the first rising time is shorter than the second rising time.

2. The display device as claimed in claim 1 , wherein a slew rate of the first clock signal is greater than the slew rate of the second clock signal.

3. The display device as claimed in claim 1 , wherein:
the first clock signal has a first falling time,
the second clock signal has a second falling time, and
the first falling time is shorter than the second falling time.

4. The display device as claimed in claim 1 , wherein:
the first clock signal has a first maximum voltage and a first minimum voltage lower than the first maximum voltage,
the second clock signal has a second maximum voltage and a second minimum voltage lower than the second maximum voltage,
the first maximum voltage is lower than the second maximum voltage, and
the first minimum voltage is lower than the second minimum voltage.

5. The display device as claimed in claim 1 , wherein the display panel includes a display area to display an image and a non-display area outside the display area.

6. The display device as claimed in claim 5 , wherein:
the display area includes 1st to nth pixel rows (n is a natural number of 2 or more), and
the active section is a vertical active section in which the data signal is input to the 1st to nth pixel rows.

7. The display device as claimed in claim 5 , wherein:
the display area includes 1st to nth pixel columns (n is a natural number of 2 or more), and
the active section is a horizontal active section in which the data signal is input to the 1st to nth pixel columns.

8. The display device as claimed in claim 1 , wherein the timing controller is to change the first rising time to generate the second clock signal when the active section is converted to the blank section.

9. The display device as claimed in claim 1 , wherein:
the timing controller includes a first output and a second output connected with the driver,
the first output is to provide the first clock signal to the driver during the active section, and
the second output is to provide the second clock signal to the driver during the blank section.

10. A display device, comprising:
a display panel including a display area to display an image and a non-display area outside the display area;
a driver connected with the display panel through a plurality of signal lines; and
a time controller to provide a first clock signal to the driver during an active section and a second clock signal to the driver during a blank section adjacent to the active section, wherein the driver is to provide a data signal generated based on the first clock signal and the second clock signal to the signal lines during the active section, and wherein a slew rate of the first clock signal is greater than a slew rate of the second clock signal.

11. The display device as claimed in claim 10 , wherein a rising time of the first clock signal is shorter than the rising time of the second clock signal.

12. The display device as claimed in claim 10 , wherein the driver is to provide a dummy data signal generated based on the first clock signal and the second clock signal to the non-display area during the blank section.

13. The display device as claimed in claim 10 , wherein:
the display area includes 1st to nth pixel rows (n is a natural number of 2 or more), and
the active section is a vertical active section in which the data signal is input to the 1st to nth pixel rows.

14. The display device as claimed in claim 10 , wherein:
the display area includes 1st to nth pixel columns (n is a natural number of 2 or more), and
the active section is a horizontal active section in which the data signal is input to the 1st to nth pixel columns.

15. The display device as claimed in claim 10 , wherein the timing controller is to adjust a slew rate of the first clock signal to generate the second clock signal when the active section is converted to the blank section.

16. The display device as claimed in claim 10 , wherein:
the timing controller includes a first output and a second output connected with the driver,
the first output is to provide the first clock signal to the driver during the active section, and
the second output is to provide the second clock signal to the driver during the blank section.

17. The display device as claimed in claim 10 , wherein:
the first clock signal has a first maximum voltage and a first minimum voltage lower than the first maximum voltage,
the second clock signal has a second maximum voltage and a second minimum voltage lower than the second maximum voltage,
the first maximum voltage is lower than the second maximum voltage, and
the first minimum voltage is lower than the second minimum voltage.

18. A method for driving a display device, comprising:
providing a first clock signal having a first rising time to a driver during an active section in which a data signal displaying an image is input; and
providing a second clock signal having a second rising time to the driver during a blank section located adjacent to the active section, wherein the first rising time is shorter than the second rising time.

19. The method as claimed in claim 18 , wherein a slew rate of the first clock signal is greater than a slew rate of the second clock signal.

20. The method as claimed in claim 18 , wherein:
the first clock signal has a first maximum voltage and a first minimum voltage lower than the first maximum voltage,
the second clock signal has a second maximum voltage and a second minimum voltage lower than the second maximum voltage,
the first maximum voltage is lower than the second maximum voltage, and
the first minimum voltage is lower than the second minimum voltage.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Dong In
• Park Jin Kyu
• Lee Yo Han
• Choi Ki Hoon
• Hong Hyun Seok

Classifications

• G09G5/32

  with means for controlling the display position {(see provisionally G09G5/42)} · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G2300/0413

  Details of dummy pixels or dummy lines in flat panels · CPC title

• G09G5/28 Primary

  for enhancement of character form, e.g. smoothing · CPC title

• G09G5/003 Primary

  Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto (specific for a CRT G09G1/165; for a flat panel G09G3/2092) · CPC title