System and method for dynamically adjusting voltage frequency

Patent metadata

Field	Value
Publication number	US-10606335-B2
Application number	US-201415510266-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Dec 12, 2014
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

A dynamic voltage frequency scaling (DVFS) system is provided. The DVFS system includes: a computation unit, a power management unit (PMU), a hardware activity monitor (HAM), and a hardware voltage monitor (HVM). The HAM monitors a working status and temperature information of the computation unit, and determines whether to update an operating voltage and frequency of the computation unit according to the working status, the temperature information, and a previous determination result. When the HAM determines to update the operating voltage and frequency, the HAM generates a first control signal to the PMU to calibrate the operating voltage and frequency. The HVM detects timing information of the computation unit and determine whether to fine-tune the operating voltage according to the detected timing information. When the HVM determines to fine-tune the operating voltage, the hardware monitor generates a second control signal to the PMU to fine-tune the operating voltage.

First claim

What is claimed is:

1. A dynamic voltage frequency scaling (DVFS) system, comprising:
a computation unit;
a power management unit;
a hardware activity monitor circuit, configured to monitor a working status and temperature information of the computation unit, and determine whether to update an operating voltage and an operating frequency of the computation unit according to the working status, the temperature information, and a previous DVFS determination result, wherein when the hardware activity monitor circuit determines to update the operating voltage and operating frequency of the computation unit, the hardware activity monitor circuit generates a first control signal to the power management unit to calibrate the operating voltage and the operating frequency; and
a hardware voltage monitor circuit, configured to detect timing information of the computation unit and determine whether to tune the operating voltage according to the detected timing information,
wherein when the hardware voltage monitor circuit determines to tune the operating voltage, the hardware voltage monitor circuit generates a second control signal to the power management unit to tune the operating voltage,
wherein the hardware voltage monitor comprises:
a status register;
a detection circuit, configured to detect timing information of the computation unit
a status determination circuit, configured to determine whether the timing information complies with the operating voltage;
a timer circuit, wherein the timer circuit starts to measure time every time the power management unit has completed calibration of the operating voltage and the operating frequency of the computation unit according to the first control signal;
a time-out determination circuit and
a decoding circuit, configured to determine whether to tune the operating voltage of the computation unit according to a current adaptive-voltage-scaling (AVS) determination result generated by the time-out determination circuit and a previous AVS determination result stored in the status register,
wherein when the status determination circuit determines that the timing information complies with the operating voltage, the time-out determination circuit determines whether the timing information consistently complies with the operating voltage during a current detection period,
if so, the time-out determination circuit sets the current AVS determination result as a pass and stores the current AVS determination result to the status register,
if not, the time-out determination circuit sets the current AVS determination result as a failure, and stores the current AVS determination result to the status register,
wherein when the decoding circuit determines to tune the operating voltage of the computation unit, the decoding circuit generates the second control signal to the power management unit to tune the operating voltage,
wherein when the decoding circuit determines that both the current AVS determination result and the previous AVS determination result are a pass, the second control signal generated by the decoding circuit controls the power management unit to decrease the operating voltage,
wherein when the decoding circuit determines that the current AVS determination result is a pass and the previous AVS determination result is a failure, the decoding circuit does not tune the operating voltage,
wherein when the decoding circuit determines that the current AVS determination result is a failure, the second control signal generated by the decoding circuit controls the power management unit to increase the operating voltage.

2. The system as claimed in claim 1 , wherein the computation unit comprises one or more processors.

3. The system as claimed in claim 1 , wherein the working status indicates workload information of the computation unit.

4. The system as claimed in claim 3 , wherein the hardware activity monitor circuit comprises:
an event counting circuit configured to detect the workload information of the computation unit;
a workload computation circuit, configured to compare the workload information with a predetermined threshold to generate a workload determination result; and
a calibration prediction circuit, configured to generate a current DVFS determination result according to the workload determination result, the temperature information, and a current configuration, and determine whether to update the operating voltage and the operating frequency of the computation unit by determining the relationship between the current DVFS determination result and the previous DVFS determination result;
wherein when the calibration prediction circuit determines to update the operating voltage and the operating frequency of the computation unit, the calibration prediction circuit generates the first control signal to the power management unit to calibrate the operating voltage and the operating frequency of the computation unit.

5. The system as claimed in claim 4 , wherein when the calibration prediction circuit determines that both the current DVFS determination result and the previous DVFS determination result are a pass, the calibration prediction circuit determines to decrease the operating voltage and the operating frequency of the computation unit,
wherein when the calibration prediction circuit determines that the current DVFS determination result is a failure, the calibration prediction circuit determines to increase the operating voltage and the operating frequency of the computation unit.

6. The system as claimed in claim 1 , wherein the detection circuit and the computation unit is within the same voltage domain.

7. The system as claimed claim 1 , wherein the power management unit comprises:
a dynamic voltage frequency scaling circuit, configured to calibrate the operating voltage and the operating frequency of the computation unit according to the first control signal;
an adaptive voltage scaling circuit , configured to tune the operating voltage of the computation unit according to the second control signal;
a phase-locked loop circuit, configured to provide the operating frequency to the computation unit; and
a power management integrated circuit, configured to provide the operating voltage to the computation unit.

8. A dynamic voltage frequency scaling (DVFS) method, for use in a dynamic voltage frequency scaling system, wherein the dynamic voltage frequency scaling system comprises a computation unit, a hardware activity monitor circuit, a hardware voltage monitor circuit, and a power management unit, the method comprising:
utilizing the hardware activity monitor circuit to monitor a working status and temperature information of the computation unit;
utilizing the hardware activity monitor circuit to determine whether to update an operating voltage and an operating frequency of the computation unit according to the working status, the temperature information, and a previous DVFS determination result;
utilizing the hardware activity monitor circuit to generate a first control signal to the power management unit to calibrate the operating voltage and the operating frequency when the hardware activity monitor circuit determines to update the operating voltage and the operating frequency;
utilizing the hardware voltage monitor circuit to detect timing information of the computation unit and determine whether to tune the operating voltage according to the timing information; and
utilizing the hardware voltage monitor circuit to generate a second control signal to the power management unit to calibrate the operating voltage when the hardware voltage monitor circuit determines to tune the operating voltage,
wherein the hardware voltage monitor circuit comprises a status register, a detecti

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Gu Deming
• Hong Zhou

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02D10/172

  Cross-Sectional Technologies · mapped topic

• Y02D10/126

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title