Information processing apparatus for determining level of power saving of processor according to return time notified by device connected to processor, and power saving method for processor

Patent metadata

Field	Value
Publication number	US-10606334-B2
Application number	US-201816201908-A
Country	US
Kind code	B2
Filing date	Nov 27, 2018
Priority date	May 25, 2016
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

An information processing apparatus includes a processor and a first device. The processor executes an operating system and a power control application, which operates on the operating system and controls a power mode of the information processing apparatus. The first device is connected to the processor to communicate with the processor, and notifies the operating system of a return time. The power control application notifies the first device of information indicating the power mode of the information processing apparatus. Based on the information notified by the power control application, the first device determines a return time of which the operating system is to be notified, and notifies the operating system of the determined return time. Based on the return time notified by the first device, the operating system determines a power saving state to which the processor is to shift, and shifts the processor to the determined power saving state.

First claim

What is claimed is:

1. An information processing apparatus comprising:
a processor configured to execute a power control application to control a power mode of the information processing apparatus and execute a device driver for a PCIe (Peripheral Component Interconnect Express) device configured to communicate with the processor via a PCIe bus; and
the PCIe device,
wherein the power control application executed by the processor is configured to notify the PCIe device of the power mode of the information processing apparatus, and
wherein, when the PCIe device receives the power mode of the information processing apparatus, the PCIe device then notifies the device driver executed by the processor of return time information via the PCIe bus, and the processor shifts to a power state determined based on at least the return time information.

2. The information processing apparatus according to claim 1 , wherein the PCIe device is a first PCIe device, the information processing apparatus further comprising a second PCIe device configured to communicate with the processor via a PCIe bus,
wherein the power control application executed by the processor is configured to notify, the first PCIe device and the second PCIe device of the power mode of the information processing apparatus, and
wherein, when the first PCIe device and the second PCIe device receive the power mode of the information processing apparatus, the first PCIe device and the second PCIe device notifies the device driver executed by the processor of return time information via the PCIe bus, and the processor shifts to a power state determined based on at least the return time information from the first PCIe device and the return time information from the second PCIe device.

3. The information processing apparatus according to claim 2 , wherein the second PCIe device is a network interface configured to receive data from an external apparatus via a network.

4. The information processing apparatus according to claim 3 , wherein, based on the power mode of the information processing apparatus and a device status of the second PCIe device, the second PCIe device notifies the processor of return time information.

5. The information processing apparatus according to claim 1 , wherein the PCIe device includes a universal serial bus (USB) interface and, based on presence or absence of a link to the USB interface, notifies the device driver executed by the processor of the return time information.

6. The information processing apparatus according to claim 2 , wherein the processor shifts to the power state determined based on a shorter time among the return time information from the first PCIe device and the return time information from the second PCIe device.

7. The information processing apparatus according to claim 1 ,
wherein, in a case where the power mode indicates a first power mode, the PCIe device notifies the processor of first return time information, and
wherein, in a case where the power mode information indicates a second power mode where more power is saved than in the first power mode, the PCIe device notifies the processor of second return time information indicating a longer time than the first return time information.

8. The information processing apparatus according to claim 1 , wherein the PCIe device notifies the device driver executed by the processor of the return time information via the PCIe bus.

9. The information processing apparatus according to claim 1 , wherein the PCIe device executes Latency Tolerance Reporting (LTR) to notify the device driver executed by the processor of the return time information.

10. The information processing apparatus according to claim 1 , wherein the PCIe device has a table in which the power mode of the information processing apparatus is associated with the return time information.

11. The information processing apparatus according to claim 1 , further comprising a printing unit configured to perform printing.

12. The information processing apparatus according to claim 11 , wherein the PCIe device is an image processing unit configured to execute image processing on an image to be printed by the printing unit.

13. The information processing apparatus according to claim 12 ,
wherein, in a case where a device status of the PCIe device is a normal power state, the PCIe device notifies, based on the power mode of the information processing apparatus, first return time information, and
wherein, in a case where the device status of the PCIe device is a power saving state where more power is saved than in the normal power state, the PCIe device notifies, based on the power mode of the information processing apparatus, second return time information.

14. The information processing apparatus according to claim 1 , wherein, based on at least the power mode of the information processing apparatus and a device status of the PCIe device, the PCIe device notifies the return time information.

15. A power control method for an information processing apparatus having a processor configured to execute a power control application to control a power mode of the information processing apparatus and execute a device driver for a PCIe (Peripheral Component Interconnect Express) device configured to communicate with the processor via a PCIe bus, the power control method comprising:
notifying, by the power control application executed by the processor, the PCIe device of the power mode of the information processing apparatus;
notifying, by the PCIe device when the PCIe device receives the power mode of the information processing apparatus, the device driver executed by the processor of return time information via the PCIe bus; and
shifting the processor to a power state determined based on at least the return time information.

Assignees

• Canon Kk

Inventors

• Hashimoto Minoru

Classifications

• H04N1/00933

  Timing control or synchronising (H04N1/00928, H04N1/00931, H04N1/00954 and H04N1/0096 take precedence) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F1/3228

  Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands · CPC title

• G06F13/102 Primary

  where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

• G06F1/3215 Primary

  Monitoring of peripheral devices · CPC title