Virtual lookup table for probabilistic constellation shaping

Patent metadata

Field	Value
Publication number	US-10601629-B2
Application number	US-201816055989-A
Country	US
Kind code	B2
Filing date	Aug 6, 2018
Priority date	Aug 9, 2017
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

Probabilistic generation and decoding modulation symbols for use with optical communication. Codewords are generated using combinations of symbols from a modulation symbol alphabet, and each type of modulation symbol is sequentially generated using a hardware efficient combination generator that performs as a virtual lookup table (LUT). Likewise, decoding can be performed by sequentially identifying locations of individual modulation symbols within the received codeword.

First claim

What is claimed is:

1. A method for probabilistic generation of modulation symbols implemented by processing circuitry, the method comprising:
receiving, from an information source device, a plurality of bits having an arbitrary distribution;
partitioning the plurality of bits into a plurality of bit sets based on a symbol length of a codeword and a modulation constellation defined by a modulation symbol alphabet;
mapping a first bit set of the plurality of bit sets based on a first power symbol of the modulation symbol alphabet to produce a plurality of first modulation symbols;
populating an output codeword at a plurality of first codeword locations with the plurality of first modulation symbols;
mapping a second bit set of the plurality of bit sets based on a second power symbol of the modulation symbol alphabet to produce a plurality of second modulation symbols;
populating a plurality of remaining codeword locations with the plurality of second modulation symbols; and
providing the output codeword for transmission.

2. The method of claim 1 , wherein the symbol length for the codeword is based on a floor determination for each of a plurality of modulation-type sequences.

3. The method of claim 1 , wherein the first power symbol is a lower power modulation symbol and the second power symbol is a higher power modulation symbol relative to the lower power modulation symbol.

4. The method of claim 1 , wherein the plurality of first modulation symbols and the plurality of second modulation symbols are real values and the codeword relates to an in-phase branch of an in-phase/quadrature modulator.

5. The method of claim 1 , wherein the plurality of first modulation symbols and the plurality of second modulation symbols are real values and the codeword relates to a quadrature branch of an in-phase/quadrature modulator.

6. The method of claim 1 , wherein the plurality of first modulation symbols and the plurality of second modulation symbols are complex values and the codeword relates to an in-phase branch and a quadrature branch of an in-phase/quadrature modulator.

7. The method of claim 1 , wherein the plurality of bits are generated by the information source device.

8. An apparatus for a virtual lookup table for probabilistic generation of modulation symbols, the apparatus comprising:
processor circuitry configured to:
receive, from an information source device, a plurality of bits having an arbitrary distribution;
partition the plurality of bits into a plurality of bit sets based on a symbol length of a codeword and a modulation constellation defined by a modulation symbol alphabet;
map a first bit set of the plurality of bit sets based on a first power symbol of the modulation symbol alphabet to produce a plurality of first modulation symbols;
populate an output codeword at a plurality of first codeword locations with the plurality of first modulation symbols;
map a second bit set of the plurality of bit sets based on a second power symbol of the modulation symbol alphabet to produce a plurality of second modulation symbols;
populate a plurality of remaining codeword locations with the plurality of second modulation symbols; and
provide the output codeword for transmission.

9. The apparatus of claim 8 , wherein the symbol length for the codeword is based on a floor determination for each of a plurality of modulation-type sequences.

10. The apparatus of claim 8 , wherein the first power symbol is a lower power modulation symbol and the second power symbol is a higher power modulation symbol relative to the lower power modulation symbol.

11. The apparatus of claim 8 , wherein the plurality of first modulation symbols and the plurality of second modulation symbols are real values and the codeword relates to an in-phase branch of an in-phase/quadrature modulator.

12. The apparatus of claim 8 , wherein the plurality of first modulation symbols and the plurality of second modulation symbols are real values and the codeword relates to a quadrature branch of an in-phase/quadrature modulator.

13. The apparatus of claim 8 , wherein the plurality of first modulation symbols and the plurality of second modulation symbols are complex values and the codeword relates to an in-phase branch and a quadrature branch of an in-phase/quadrature modulator.

14. The apparatus of claim 8 , wherein the plurality of bits are provided by the information source device.

15. The apparatus of claim 8 , wherein the processor circuitry is further configured to provide the output codeword for transmission with forward error correction (FEC).

16. A method for decoding a block of modulation symbols, comprising:
receiving a codeword, the codeword including a plurality of codeword locations populated by a plurality of modulation symbols based on a plurality of modulation symbol alphabets;
determining a first plurality of codeword locations for a first plurality of modulation symbols based on a first one of the plurality of modulation symbol alphabets for lower power modulation symbols;
determining a second plurality of codeword locations for a second plurality of modulation symbols based on a second one of the plurality of modulation symbol alphabets for higher power modulation symbols relative to the lower power modulation symbols for the first one of the plurality of modulation symbol alphabets; and
decoding the first plurality of modulation symbols and the second plurality of modulation symbols to produce a bit string.

17. The method of claim 16 , wherein the plurality of modulation symbols are real values and the codeword relates to an in-phase branch of an in-phase/quadrature modulator.

18. The method of claim 16 , wherein the plurality of modulation symbols are real values and the codeword relates to a quadrature branch of an in-phase/quadrature modulator.

19. The method of claim 16 , wherein the plurality of modulation symbols are complex values and the codeword relates to an in-phase branch and a quadrature branch of an in-phase/quadrature modulator.

Assignees

• Futurewei Technologies Inc

Inventors

• Krishnan Murali
• Cui Yan
• Bai Yu Sheng

Classifications

• H04L27/362 Primary

  Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated (H04L27/366 takes precedence) · CPC title

• H04L27/3411

  reducing the peak to average power ratio or the mean power of the constellation; Arrangements for increasing the shape gain of a signal set · CPC title

• H04L1/0052

  Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables · CPC title

• H04L1/0043 Primary

  Realisations of complexity reduction techniques, e.g. use of look-up tables · CPC title

• H04L27/0008

  arrangements for allowing a transmitter or receiver to use more than one type of modulation (negotiating modulation type for two-way transmission paths H04L5/1453) · CPC title