Methods and apparatus for dynamic adjustment of amplifier gain

Patent metadata

Field	Value
Publication number	US-10601628-B2
Application number	US-201815979163-A
Country	US
Kind code	B2
Filing date	May 14, 2018
Priority date	May 14, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

An aspect of the present disclosure includes methods, systems, and computer-readable media for triggering the single signal during the first buffer period to concurrently adjust a first plurality of gain states of a first plurality of low-noise amplifiers associated with a first expected reception of the first symbol on the first component carrier and a second plurality of gain states of a second plurality of low-noise amplifiers associated with a second expected reception of the second symbol on the second component carrier, and receiving the first symbol via the first component carrier and the second symbol via the second component carrier after the first buffer period.

First claim

What is claimed is:

1. A method of wireless communication, comprising:
determining a first time at which a first symbol is to be received after a first buffer period on a first component carrier;
determining a second time at which a second symbol is to be received after a second buffer period on a second component carrier;
associating a single signal with a first reception operation of the first component carrier and a second reception operation of the second component carrier in response to the first buffer period substantially overlapping the second buffer period;
triggering the single signal during the first buffer period to concurrently adjust a first plurality of gain states of a first plurality of low-noise amplifiers associated with a first expected reception of the first symbol on the first component carrier and a second plurality of gain states of a second plurality of low-noise amplifiers associated with a second expected reception of the second symbol on the second component carrier; and
receiving the first symbol via the first component carrier and the second symbol via the second component carrier after the first buffer period.

2. The method of claim 1 , wherein triggering the single signal further includes communicating the single signal to the first plurality of low-noise amplifiers and the second plurality of low-noise amplifiers on a radio frequency front end bus.

3. The method of claim 1 , wherein the single signal includes a radio-frequency front end reconfigurable trigger signal.

4. The method of claim 1 , wherein the first component carrier includes a first plurality of diversity paths and the second component carrier includes a second plurality of diversity paths.

5. The method of claim 4 , wherein each diversity path includes one or more low-noise amplifiers from the first plurality of low-noise amplifiers or the second plurality of low-noise amplifiers.

6. The method of claim 1 , further comprising detecting, after receiving the first symbol and the second symbol, a timing difference between the first component carrier and the second component carrier, wherein the timing difference indicates that a first subsequent buffer period of the first component carrier does not substantially overlap with a second subsequent buffer period of the second component carrier.

7. The method of claim 6 , further comprising:
determining a third time at which a third symbol is to be received after a third buffer period on a first component carrier;
determining a fourth time at which a fourth symbol is to be received after a fourth buffer period on a third component carrier, the third component carrier being associated with a single second signal;
associating the second single signal with the first reception operation of the first component carrier in response to the third buffer period substantially overlapping the fourth buffer period;
triggering the second signal during the third buffer period to concurrently adjust the first plurality of gain states of the first plurality of low-noise amplifiers associated with a third expected reception of the third symbol on the first component carrier and a third plurality of gain states of a third plurality of low-noise amplifiers associated with a fourth expected reception of the fourth symbol on the third component carrier; and
receiving the third symbol via the first component carrier and the fourth symbol via the third component carrier after the third buffer period.

8. A device for wireless communications, comprising
a memory;
a transceiver; and
one or more processors operatively coupled to the memory and the transceiver, the one or more processors being configured to:
determine a first time at which a first symbol is to be received after a first buffer period on a first component carrier;
determine a second time at which a second symbol is to be received after a second buffer period on a second component carrier;
associate a single signal with a first reception operation of the first component carrier and a second reception operation of the second component carrier in response to the first buffer period substantially overlapping the second buffer period;
trigger the single signal during the first buffer period to concurrently adjust a first plurality of gain states of a first plurality of low-noise amplifiers associated with a first expected reception of the first symbol on the first component carrier and a second plurality of gain states of a second plurality of low-noise amplifiers associated with a second expected reception of the second symbol on the second component carrier; and
receive, via the transceiver, the first symbol via the first component carrier and the second symbol via the second component carrier after the first buffer period.

9. The device of claim 8 , wherein triggering the single signal further includes communicating the single signal to the first plurality of low-noise amplifiers and the second plurality of low-noise amplifiers on a radio frequency front end bus.

10. The device of claim 8 , wherein the single signal includes a radio-frequency front end reconfigurable trigger signal.

11. The device of claim 8 , wherein the first component carrier includes a first plurality of diversity paths and the second component carrier includes a second plurality of diversity paths.

12. The device of claim 8 , wherein each diversity path includes one or more low-noise amplifiers from the first plurality of low-noise amplifiers or the second plurality of low-noise amplifiers.

13. The device of claim 8 , wherein the one or more processors are further configured to detect, after receiving the first symbol and the second symbol, a timing difference between the first component carrier and the second component carrier, wherein the timing difference indicates that a first subsequent buffer period of the first component carrier does not substantially overlap with a second subsequent buffer period of the second component carrier.

14. The device of claim 13 , wherein the one or more processors are further configured to:
determine a third time at which a third symbol is to be received after a third buffer period on a first component carrier;
determine a fourth time at which a fourth symbol is to be received after a fourth buffer period on a third component carrier, the third component carrier being associated with a single second signal;
associate the second single signal with the first reception operation of the first component carrier in response to the third buffer period substantially overlapping the fourth buffer period;
trigger the second signal during the third buffer period to concurrently adjust the first plurality of gain states of the first plurality of low-noise amplifiers associated with a third expected reception of the third symbol on the first component carrier and a third plurality of gain states of a third plurality of low-noise amplifiers associated with a fourth expected reception of the fourth symbol on the third component carrier; and
receive, via the transceiver, the third symbol via the first component carrier and the fourth symbol via the third component carrier after the third buffer period.

15. The device of claim 8 , wherein the device is a user equipment.

16. The device of claim 8 , wherein the device is a base station.

17. A non-transitory computer-readable medium having instructions stored therein that, when executed by one or more processors of a local device, cause the one or more processors to:
determine a first time at which a first symbol is to be received after a first b

Assignees

• Qualcomm Inc

Inventors

• Lie Gregory
• O'Shea Helena Deirdre
• Zhu Haidong
• Zhao Jason
• George Brian
• Shen Xiaoling

Classifications

• H04L5/0044

  Allocation of payload; Allocation of data channels, e.g. PDSCH or PUSCH · CPC title

• H04L27/2662 Primary

  Symbol synchronisation · CPC title

• H03F3/189

  High-frequency amplifiers, e.g. radio frequency amplifiers · CPC title

• H04L5/0078

  Timing of allocation · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title