Alternately updated digital to analog converters

Patent metadata

Field	Value
Publication number	US-10601438-B2
Application number	US-201916434526-A
Country	US
Kind code	B2
Filing date	Jun 7, 2019
Priority date	Jun 7, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A modulator of an analog to digital converter includes a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate. The modulator further includes a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate. The modulator further includes a second DAC configured to generate second DAC output at half the sample rate, where the first DAC and the second DAC are updated at alternate cycles of the clock input.

First claim

What is claimed is:

1. A modulator of an analog to digital converter, the modulator comprising:
a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate;
a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate; and
a second DAC configured to generate second DAC output at half the sample rate, wherein the first DAC and the second DAC are updated at alternate cycles of the clock input.

2. The modulator of claim 1 , wherein the first DAC is configured to receive values of the digital signal generated by the quantizer in response to odd pulses of the clock input, and wherein the second DAC is configured to receive values of the digital signal generated by the quantizer in response to even pulses of the clock input.

3. The modulator of claim 1 , wherein the quantizer is configured to generate the digital signal based on a filtered difference between an input analog signal and a combination of the first DAC output and the second DAC output.

4. The modulator of claim 3 , further comprising a loop filter configured to generate the filtered difference.

5. The modulator of claim 4 , wherein the loop filter includes an integrator.

6. The modulator of claim 1 , wherein the first DAC is configured to generate the first DAC output to include pulses as wide as two pulses of the clock input, and wherein the second DAC is configured to generate the second DAC output to include pulses as wide as two pulses of the clock input.

7. The modulator of claim 1 , further comprising:
a first flip-flop device configured to receive a first portion of the digital signal from the quantizer, the first flip-flop device clocked by odd pulses of the clock input, wherein the first DAC is configured to generate the first DAC output based on a first signal received from the first flip-flop device; and
a second flip-flop device configured to receive a second portion of the digital signal from the quantizer, the second flip-flop device clocked by even pulses of the clock input, wherein the second DAC is configured to generate the second DAC output based on a second signal received from the second flip-flop device.

8. The modulator of claim 7 , wherein the quantizer includes:
a first quantizer component clocked by the odd pulses of the clock input and configured to generate the first portion of the digital signal; and
a second quantizer component by the even pulses of the clock input and configured to generate the second portion of the digital signal.

9. A modulator of an analog to digital converter, the modulator comprising:
a quantizer component configured to generate a digital signal based on a clock input;
a first digital to analog converter (DAC) configured to generate first DAC output including pulses as wide as two pulses of the clock input; and
a second DAC configured to generate second DAC output including pulses as wide as two pulses of the clock input.

10. The modulator of claim 9 , wherein the first DAC is configured to receive values of the digital signal generated by the quantizer in response to odd pulses of the clock input, and wherein the second DAC is configured to receive values of the digital signal generated by the quantizer in response to even pulses of the clock input.

11. The modulator of claim 9 , wherein the quantizer is configured to generate the digital signal based on a filtered difference between an input analog signal and a combination of the first DAC output and the second DAC output.

12. The modulator of claim 11 , further comprising a loop filter configured to generate the filtered difference.

13. The modulator of claim 12 , wherein the loop filter includes an integrator.

14. The modulator of claim 9 , further comprising:
a first flip-flop device configured to receive a first portion of the digital signal from the quantizer, the first flip-flop device clocked by odd pulses of the clock input, wherein the first DAC is configured to generate the first DAC output based on a first signal received from the first flip-flop device; and
a second flip-flop device configured to receive a second portion of the digital signal from the quantizer, the second flip-flop device clocked by even pulses of the clock input, wherein the second DAC is configured to generate the second DAC output based on a second signal received from the second flip-flop device.

15. The modulator of claim 14 , wherein the quantizer includes:
a first quantizer component clocked by the odd pulses of the clock input and configured to generate the first portion of the digital signal; and
a second quantizer component by the even pulses of the clock input and configured to generate the second portion of the digital signal.

16. A transceiver comprising:
a receiver; and
an analog digital converter (ADC) coupled to the receiver, the ADC including:
a modulator component comprising:
a quantizer component configured to generate a digital signal based on a clock input operating at a sample rate;
a first digital to analog converter (DAC) configured to generate first DAC output at half the sample rate; and
a second DAC configured to generate second DAC output at half the sample rate, wherein the first DAC and the second DAC are updated at alternate cycles of the clock input.

17. The transceiver of claim 16 , wherein the first DAC is configured to receive values of the digital signal generated by the quantizer in response to odd pulses of the clock input, and wherein the second DAC is configured to receive values of the digital signal generated by the quantizer in response to even pulses of the clock input.

18. The transceiver of claim 16 , wherein the quantizer is configured to generate the digital signal based on a filtered difference between an input analog signal and a combination of the first DAC output and the second DAC output.

19. The transceiver of claim 18 , wherein the modulator component further includes a loop filter configured to generate the filtered difference.

20. The transceiver of claim 16 , wherein the first DAC is configured to generate the first DAC output to include pulses as wide as two pulses of the clock input, and wherein the second DAC is configured to generate the second DAC output to include pulses as wide as two pulses of the clock input.

21. A modulator of an analog to digital converter, the modulator comprising:
a quantizer component configured to generate a digital signal based on a clock input;
a first digital to analog converter (DAC) configured to receive input from a first exclusive or (XOR) device, the first XOR device receiving odd pulses of the clock input and odd values of the digital signal; and
a second DAC configured to generate second DAC configured to receive input from a second XOR device, the second XOR device receiving even pulses of the clock input and even values of the digital signal.

22. The modulator of claim 21 , further comprising an integrator configured to generate an integrated signal based on a difference between output of a cascade of integrators and a sum of output of the first DAC and output of the second DAC, the quantizer configured to generate digital signal based on the integrated signal.

Assignees

• Texas Instruments Inc

Inventors

• Miglani Eeshan
• Pentakota Visvesvaraya Appala

Classifications

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H04B1/40

  Circuits · CPC title

• H03M3/42

  having multiple quantisers arranged in parallel loops · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03M3/464 Primary

  Details of the digital/analogue conversion in the feedback path · CPC title