Apparatus for calibrating a time-interleaved analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-10601434-B1
Application number	US-201916369237-A
Country	US
Kind code	B1
Filing date	Mar 29, 2019
Priority date	Mar 29, 2019
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

An apparatus for calibrating a time-interleaved analog-to-digital converter including a plurality of time-interleaved analog-to-digital converter circuits is provided. The apparatus includes an analog signal generation circuit configured to generate an analog calibration signal based on a digital calibration signal representing one or more digital data sequences for calibration. The analog calibration signal is a wideband signal. Further, the apparatus includes a coupling circuit configured to controllably couple an input node of the time-interleaved analog-to-digital converter to either the analog signal generation circuit or to a node capable of providing an analog signal for digitization.

First claim

What is claimed is:

1. An apparatus for calibrating a time-interleaved analog-to-digital converter comprising a plurality of time-interleaved analog-to-digital converter circuits, the apparatus comprising:
an analog signal generation circuit configured to generate an analog calibration signal based on a digital calibration signal representing one or more digital data sequences for calibration, wherein the analog calibration signal is a wideband signal; and
a coupling circuit configured to operably couple an input node of the time-interleaved analog-to-digital converter to either the analog signal generation circuit or to a node configured to provide an analog signal for digitization.

2. The apparatus of claim 1 , wherein the coupling circuit is configured to controllably couple the input node of the time-interleaved analog-to-digital converter to either the analog signal generation circuit or to the signal node based on a control signal indicative of a redetermined operation mode of the time-interleaved analog-to-digital converter.

3. The apparatus of claim 1 , wherein a bandwidth of the analog calibration signal is less than half of a maximum value of the sample rate of the time-interleaved analog-to-digital converter.

4. The apparatus of claim 1 , wherein amplitude values of the analog calibration signal cover all input amplitude values supported by the time-interleaved analog-to-digital converter.

5. The apparatus of claim 1 , wherein a linearity of the analog signal generation circuit is higher than a desired linearity of the time-interleaved analog-to-digital converter.

6. The apparatus of claim 1 , wherein the analog signal generation circuit comprises:
a digital-to-analog converter configured to generate an analog signal based on the digital calibration signal; and
an analog filter configured to generate the analog calibration signal by filtering the analog signal.

7. The apparatus of claim 6 , wherein the analog filter comprises:
an analog finite impulse response filter configured to generate an auxiliary analog signal by filtering the analog signal; and
a passive analog filter coupled to the analog finite impulse response filter and configured to generate the analog calibration signal by filtering the auxiliary analog signal.

8. The apparatus of claim 6 , wherein the digital-to-analog converter exhibits a resolution of 1 bit.

9. The apparatus of claim 1 , wherein the analog signal generation circuit comprises:
delay circuit configured to iteratively delay a digital data sequence represented by the digital calibration signal for generating a plurality of delayed digital data sequences;
a plurality of digital-to-analog converters each configured to generate a respective analog signal based on one of the plurality of delayed digital data sequences;
a combiner configured to combine the analog signals generated by the plurality of digital-to-analog converters to an auxiliary analog signal; and
a passive analog filter coupled to the combiner and configured to generate the analog calibration signal by filtering the auxiliary analog signal.

10. The apparatus of claim 9 , wherein the plurality of digital-to-analog converters are configured to generate the analog signals with different gains.

11. The apparatus of claim 9 , wherein the delay circuit is configured to iteratively delay the digital data sequence by a delay time, and wherein the delay time τ is defined as follows:

τ
=

T
s

D

,

with 1/T s denoting a data rate of the digital calibration signal, and D denoting a desired oversampling ratio for the digital calibration signal.

12. The apparatus of claim 9 , wherein the delay circuit comprises a chain of delay elements configured to iteratively delay the digital data sequence, wherein a delay time by which each of the delay elements delays its input is based on a control signal, and wherein the apparatus further comprises a delay-locked loop configured to supply the control signal to the delay elements.

13. The apparatus of claim 9 , wherein the analog signal generation circuit comprises:
a second delay circuit configured to iteratively delay a second digital data sequence represented by the digital calibration signal for generating a plurality of delayed second digital data sequences; and
a second plurality of digital-to-analog converters each configured to generate a respective second analog signal based on one of the plurality of delayed second digital data sequences,
wherein the combiner is configured to combine the analog signals generated by the plurality of digital-to-analog converters and the second analog signals generated by the second plurality of digital-to-analog converters to the auxiliary analog signal.

14. The apparatus of claim 13 , wherein the second plurality of digital-to-analog converters are configured to generate the second analog signals with different gains.

15. The apparatus of claim 13 , wherein the delay circuit and the second delay circuit are configured to iteratively delay the digital data sequence and the second digital data sequence by the same delay time.

16. The apparatus of claim 9 , wherein the plurality of digital-to-analog converters exhibits a resolution of 1 bit.

17. The apparatus of claim 1 , wherein the analog signal generation circuit comprises:
a plurality of sample circuits configured to generate a plurality of sampled signals by sampling a digital data sequence represented by the digital calibration signal based on different ones of a plurality of phase shifted clock signals;
a plurality of digital-to-analog converters each configured to generate a respective analog signal based on one of the plurality of sampled signals;
a combiner configured to combine the analog signals generated by the plurality of digital-to-analog converters to an auxiliary analog signal; and
a passive analog filter coupled to the combiner and configured to generate the analog calibration signal by filtering the auxiliary analog signal.

18. The apparatus of claim 17 , wherein the plurality of digital-to-analog converters are configured to generate the analog signals with different gains.

19. The apparatus of claim 17 , wherein the number of sample circuits is equal to a desired oversampling ratio for the digital calibration signal.

20. The apparatus of claim 17 , wherein the analog signal generation circuit further comprises:
a second plurality of sample circuits configured to generate a second plurality of sampled signals by sampling a second digital data sequence represented by the digital calibration signal based on different ones of the plurality of phase shifted clock signals;
a second plurality of digital-to-analog converters each configured to generate a respective second analog signal based on one of the second plurality of sampled signals,
wherein the combiner is configured to combine the analog signals generated by the plurality of digital-to-analog converters and the second analog signals generated by the second plurality of digital-to-analog converters to the auxiliary analog signal.

21. The apparatus of claim 20 , wherein the second plurality of digital-to-analog converters are configured to generate the second analog signals w

Assignees

• Intel Corp

Inventors

• Molina Albert
• Azadet Kameran
• Camponeschi Matteo
• Ceballos Jose Luis
• Lindholm Christian
• Shin Hundo
• Clara Martin

Classifications

• H04B1/0003 Primary

  Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain (digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00) · CPC title

• H04W88/08

  Access point devices · CPC title

• H04B1/16

  Circuits · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/1215 Primary

  using time-division multiplexing · CPC title