Buffer circuit

Patent metadata

Field	Value
Publication number	US-10601405-B2
Application number	US-201916373726-A
Country	US
Kind code	B2
Filing date	Apr 3, 2019
Priority date	Apr 12, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

The present invention discloses a buffer circuit including: a pre-driver providing a first, a second, a third and a fourth driving signals according to the voltages of voltage nodes and control signals; a voltage-detection and bias circuit providing bias voltages for an output buffer and an input buffer according to the voltages of the voltage nodes and the third driving signal; the output buffer determining conduction states of the transistors of the output buffer according to the voltages of the voltage nodes, the first and the second driving signals, and the bias voltages, and thereby outputting an output signal to a signal pad; and the input buffer determining the conduction states of the transistors of the input buffer according to the voltage of the signal pad, the voltages of the voltage nodes, the fourth driving signals, and the several bias voltages, and thereby generating an input signal.

First claim

What is claimed is:

1. A buffer circuit, comprising:
a pre-driver configured to provide driving signals according to voltages of voltage nodes, a driver output signal and control signals;
a voltage-detection and bias circuit configured to provide bias voltages for a high-voltage tolerance output buffer according to the voltages of the voltage nodes, a voltage of a signal pad and the driving signals;
the high-voltage tolerance output buffer configured to generate an output signal according to the voltages of the voltage nodes, the bias voltages and at least one of the driving signals, the high-voltage tolerance output buffer including:
PMOS transistors configured to determine conduction states of the PMOS transistors according to N bias voltage(s) of the bias voltages and at least one of the driving signals, in which the N is a positive integer; and
NMOS transistors configured to determine conduction states of the NMOS transistors according to M bias voltage(s) of the bias voltages and at least one of the driving signals, in which the M is a positive integer and the output signal is dependent on the conduction states of the PMOS transistors and the conduction states of the NMOS transistors;

the signal pad configured to output the output signal; and
a P-well bias circuit configured to provide NMOS body bias voltages for bodies of the NMOS transistors respectively.

2. The buffer circuit of claim 1 , wherein the N is greater than one and the N bias voltages are generated by N different bias circuits respectively.

3. The buffer circuit of claim 1 , wherein the M is greater than one and the M bias voltages are generated by M different bias circuits respectively.

4. The buffer circuit of claim 1 , further comprising:
an N-well bias circuit configured to provide PMOS body bias voltages for bodies of the PMOS transistors respectively.

5. The buffer circuit of claim 1 , further comprising:
a high-voltage tolerance input buffer configured to generate an input signal according to the voltages of the voltage nodes, the bias voltages, the voltage of the signal pad and at least one of the driving signals.

Assignees

• Realtek Semiconductor Corp

Inventors

• Hsu Hsin-Cheng
• Tsaur Tay-Her
• Lin Po-Ching

Classifications

• H03K19/003 Primary

  Modifications for increasing the reliability {for protection} · CPC title

• H03K17/08104

  in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence) · CPC title

• H03K3/02335

  provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title

• H03K3/356113 Primary

  using additional transistors in the input circuit · CPC title