Array substrate, data driving circuit, data driving method and display apparatus

Patent metadata

Field	Value
Publication number	US-10600382-B2
Application number	US-201615227340-A
Country	US
Kind code	B2
Filing date	Aug 3, 2016
Priority date	Feb 17, 2016
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

An array substrate, data driving circuit, data driving method and display apparatus are provided. The array substrate comprises multiple rows of first scan lines, multiple rows of second scan lines, and multiple columns of data lines. The first scan lines and the data lines define crosswise pixel regions in which pixel electrodes, common electrodes, first switch unit and second switch unit are disposed. The pixel electrode is connected to data line adjacent in first row direction through first and second terminals of first switch unit. The common electrode is connected to data line adjacent in second row direction through first and second terminals of second switch unit. The first and second scan lines are connected to control terminals of first and second switch unit within odd-numbered and even-numbered column pixel regions respectively. The amount of the data lines and the number of pins of data driving chip can be reduced.

First claim

What is claimed is:

1. An array substrate, comprising multiple rows of first scan lines and multiple columns of data lines, the multiple rows of first scan lines and the multiple columns of data lines defining crosswise several pixel regions in which a pixel electrode, a common electrode, a first switch unit and a second switch unit are disposed;
a pixel electrode within any pixel region being connected to a data line adjacent in a first row direction through a first terminal and a second terminal of the first switch unit;
a common electrode within any pixel region being connected to a data line adjacent in a second row direction through a first terminal and a second terminal of the second switch unit, and the first row direction being opposite to the second row direction; and
corresponding to the pixel regions of any row, one row of second scan lines being disposed except for one row of first scan lines,
wherein the first scan lines are connected to control terminals of a first switch unit and a second switch unit within pixel regions of odd-numbered columns; and
the second scan lines are connected to control terminals of a first switch unit and a second switch unit within pixel regions of even-numbered columns;
wherein at least one of the pixel electrode and the common electrode is a plate shaped electrode with a plurality of stripe-shaped cutouts, and a length of each of the plurality of stripe-shaped cutouts in a first direction is shorter than a length of the plate shaped electrode in the first direction, and a boundary line of each of the plurality of stripe-shaped cutouts does not overlap a boundary of the plate shaped electrode.

2. The array substrate according to claim 1 , wherein a strip-shaped pixel electrode and a strip-shaped common electrode are arranged alternately in a row direction.

3. A data driving circuit used for the array substrate according to claim 2 , comprising:
a first output sub-circuit configured to, during a level of a first scan line corresponding to pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in a first row direction pixel regions of odd-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in a second row direction pixel regions of odd-numbered columns in the row; and
a second output sub-circuit configured to, during a level of a second scan line corresponding to the pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in the first row direction, pixel regions of even-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in the second row direction, pixel regions of even-numbered columns in the row.

4. The array substrate according to claim 1 , wherein the pixel electrode and the common electrode are at least partially overlapped within any pixel region.

5. A data driving circuit used for the array substrate according to claim 4 , comprising:
a first output sub-circuit configured to, during a level of a first scan line corresponding to pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in a first row direction, pixel regions of odd-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in a second row direction, pixel regions of odd-numbered columns in the row; and
a second output sub-circuit configured to, during a level of a second scan line corresponding to the pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in the first row direction, pixel regions of even-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in the second row direction, pixel regions of even-numbered columns in the row.

6. The array substrate according to claim 1 , wherein a strip-shaped pixel electrode is located on a side of a plate-shaped common electrode that is opposite to a substrate within any pixel region.

7. A data driving circuit used for the array substrate according to claim 6 , comprising:
a first output sub-circuit configured to, during a level of a first scan line corresponding to pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in a first row direction, pixel regions of odd-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in a second row direction, pixel regions of odd-numbered columns in the row; and
a second output sub-circuit configured to, during a level of a second scan line corresponding to the pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in the first row direction, pixel regions of even-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in the second row direction, pixel regions of even-numbered columns in the row.

8. The array substrate according to claim 1 , wherein a strip-shaped common electrode is located on a side of a plate-shaped pixel electrode that is opposite to the substrate within any pixel region.

9. A data driving circuit used for the array substrate according to claim 8 , comprising:
a first output sub-circuit configured to, during a level of a first scan line corresponding to pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in a first row direction, pixel regions of odd-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in a second row direction, pixel regions of odd-numbered columns in the row; and
a second output sub-circuit configured to, during a level of a second scan line corresponding to the pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in the first row direction, pixel regions of even-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in the second row direction, pixel regions of even-numbered columns in the row.

10. The array substrate according to claim 1 , wherein the array substrate further comprises a scan driving circuit connected to all the first scan lines and all the second scan lines; the scan driving circuit is configured to output a pulse signal with an active level to a first scan line and a second scan line corresponding to the pixel regions of each row in sequence; and corresponding to the pixel regions of any row, a pulse signal on the first scan line and a pulse signal on the second scan line are staggered to each other in time.

11. A data driving circuit used for the array substrate according to claim 10 , comprising:
a first output sub-circuit configured to, during a level of a first scan line corresponding to pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in a first row direction, pixel regions of odd-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in a second row direction, pixel regions of odd-numbered columns in the row; and
a second output sub-circuit configured to, during a level of a second scan line corresponding to the pixel regions of any row being an active level, output a data voltage signal to a data line that is adjacent to, in the first row direction, pixel regions of even-numbered columns in the row, and output a common voltage signal to a data line that is adjacent to, in the second row direction, pixel regio

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Zheng Yi
• Long Jun
• Guo Lei
• Shi Lingyun

Classifications

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G2320/0219

  Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title

• G09G2300/0876

  Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes · CPC title