Image processor, for scaling image data in two directions. Computing system comprising same, and related method of operation

Patent metadata

Field	Value
Publication number	US-10600145-B2
Application number	US-201414488621-A
Country	US
Kind code	B2
Filing date	Sep 17, 2014
Priority date	Dec 13, 2013
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

An image processor comprises first scaling logic that receives image data comprising a first number of lines and generates first scaled image data by scaling down the image data in a first direction, a rotation buffer that has storage capacity for storing a second number of lines less than the first number of lines and stores the first scaled image data in a rotated state, and second scaling logic that generates second scaled image data by scaling down the first scaled image data in a second direction different from the first direction.

First claim

What is claimed is:

1. An image processor comprising:
first scaling logic that:
receives, from a system memory, image data comprising a first number of lines in a first direction, each of the first number of lines having a number of image data units in a second direction different from the first direction, and
generates first scaled image data, having a second number of lines in the first direction that is less than the first number of lines, each of the second number of lines having the number of image data units in the second direction, wherein the first scaled image data is generated by scaling down the image data in the first direction by averaging the image data and by not scaling down the image data in the second direction;

a rotation buffer that has storage capacity for storing the second number of lines and stores the first scaled image data in a rotated state; and
second scaling logic that generates second scaled image data by scaling down the first scaled image data by averaging the first scaled image data, which is stored in the rotation buffer, in the second direction, wherein
a ratio for scaling down the image data in the first direction varies depending on a burst length supported by the system memory, wherein the burst length indicates a size of data that can be read from the system memory at a time.

2. The image processor of claim 1 , wherein the first number of lines is N times greater than the second number of lines (N>1) and the first scaling logic generates the first scaled image data by scaling down the image data of the first number of lines in the first direction with a scaling ratio of 1/N.

3. The image processor of claim 2 , wherein the second scaling logic generates the second scaled image data by scaling down the first scaled image data in the second direction with the scaling ratio of 1/N.

4. The image processor of claim 1 , wherein the first direction is a horizontal direction and the second direction is a vertical direction.

5. The image processor of claim 1 , wherein the rotation buffer comprises a line memory having storage capacity for storing a maximum of the second number of lines.

6. The image processor of claim 1 , further comprising third scaling logic that receives the second scaled image data from the second scaling logic and performs additional scaling on the second scaled image data.

7. The image processor of claim 1 , further comprising a register that stores the ratio for scaling down the image data in the first direction or a ratio for scaling down the image data in the second direction.

8. The image processor of claim 1 , further comprising a write Direct Memory Access (DMA) block that receives the second scaled image data from the second scaling logic and outputs the second scaled image data to the system memory.

9. The image processor of claim 1 , further comprising an output buffer that receives the second scaled image data from the second scaling logic and outputs the second scaled image data to a display controller.

10. The image processor of claim 9 , wherein the second scaled image data is transmitted directly to the display controller without passing through the system memory.

11. The image processor of claim 1 , wherein the rotation buffer is different from the system memory.

12. A computing system comprising:
a system memory that stores a source image;
an image processor that performs a rotation/scaling-down operation on the source image; and
a system bus that connects the system memory and the image processor,
wherein the image processor comprises:
first scaling logic that:
receives image data of a first number of lines in a first direction, each of the first number of lines having a number of image data units in a second direction different from the first direction, and
generates first scaled image data, having a second number of lines in the first direction that is less than the first number of lines, each of the second number of lines having the number of image data units in the second direction, wherein the first scaled image data is generated by scaling down the image data by averaging the image data in the first direction and by not scaling down the image data in the second direction;

a rotation buffer that has storage capacity for storing the second number of lines and that stores the first scaled image data in a rotated state; and

second scaling logic that generates second scaled image data by scaling down the first scaled image data by averaging the first scaled image data, which is stored in the rotation buffer, in the second direction, wherein
a ratio for scaling down the image data in the first direction varies depending on a burst length supported by the system memory, wherein the burst length indicates a size of data that can be read from the system memory at a time.

13. The computing system of claim 12 , wherein the first number of lines is N times greater than the second number of lines (N>1), and the first scaling logic generates the first scaled image data by scaling down the image data of the first number of lines in the first direction with a scaling ratio of 1/N.

14. The computing system of claim 13 , wherein the second scaling logic generates the second scaled image data by scaling down the first scaled image data in the second direction with the scaling ratio of 1/N.

15. The computing system of claim 12 , further comprising:
a display controller that controls a display device,
wherein the second scaled image data is transmitted directly to the display controller without passing through the system memory.

16. The computing system of claim 12 , wherein the rotation buffer is different from the system memory.

17. A method comprising:
receiving, from a system memory, image data comprising a first number of lines in a first direction, each of the first number of lines having a number of image data units in a second direction different from the first direction;
generating first scaled image data, having a second number of lines that is less than the first number of lines, each of the second number of lines having the number of image data units in the second direction, wherein the first scaled image data is generated by scaling down the image data in the first direction and by not scaling down the image data in the second direction;
storing the first scaled image data in a rotation buffer that has storage capacity for storing the second number of lines and that stores the first scaled image data in a rotated state;
generating second scaled image data by scaling down the first scaled image data, which is stored in the rotation buffer, in the second direction; and
generating third scaled image data, having a third number of lines that is less than the second number of lines, by scaling down the second scaled image data, wherein
a ratio for scaling down the image data in the first direction varies depending on a burst length supported by the system memory, wherein the burst length indicates a size of data that can be read from the system memory at a time.

18. The method of claim 17 , wherein the first number of lines is N times greater than the second number of lines (N>1), and the first scaled image data is generated by scaling down the image data of the first number of lines in the first direction with a scaling ratio of 1/N.

19. The method of claim 18 , wherein the second scaled image data is generated by scaling down the first scaled image data in the second direction with the scaling ratio of 1/N.

20. The method of cl

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Sung-Chul
• Kim Min-Soo
• Kong Jae-Sop

Classifications

• G09G2340/0407

  Resolution change, inclusive of the use of different resolutions for different screen areas · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T3/606

  by memory addressing or mapping · CPC title

• H04N5/2628

  Alteration of picture size, shape, position or orientation, e.g. zooming, rotation, rolling, perspective, translation · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title