Automatic generation of via patterns with coordinate-based recurrent neural network (RNN)

Patent metadata

Field	Value
Publication number	US-10599807-B2
Application number	US-201815994396-A
Country	US
Kind code	B2
Filing date	May 31, 2018
Priority date	May 31, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts for a set of integrated circuit elements. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.

First claim

What is claimed is:

1. A computer-implemented method for generating synthetic via layout patterns by a coordinate-based Recurrent Neural Network (RNN), the method comprising:
generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts for a set of integrated circuit elements;
training, by the processor, the coordinate-based RNN with the training data set of coordinate arrays; and
generating, by the processor, using the coordinate-based RNN, new synthetic via patterns.

2. The computer-implemented method of claim 1 , further comprising manufacturing an integrated circuit using at least one of the new synthetic via patterns.

3. The computer-implemented method of claim 1 , wherein at least one of the new synthetic via patterns comprises a new pattern relative to one or more training patterns generated by the coordinate-based RNN during said training step.

4. The computer-implemented method of claim 1 , wherein the set of coordinate arrays are configured as training data for the coordinate-based RNN.

5. The computer-implemented method of claim 1 , wherein the coordinate arrays specify the center coordinates of the vias in the set of physical design layouts for the integrated circuit.

6. The computer-implemented method of claim 1 , further comprising padding any of coordinate arrays having less than a maximum possible number of vias.

7. The computer-implemented method of claim 1 , further comprising performing a design or mask rule checking process on the new synthetic via patterns.

8. The computer-implemented method of claim 1 , further comprising converting the new synthetic via patterns having a coordinate basis to another pattern format having a layout basis.

9. The computer-implemented method of claim 1 , wherein the coordinate-based RNN uses seed arrays of random numbers for pattern generation and extension relative to one or more training patterns generated by the coordinate-based RNN during said training step.

10. The computer-implemented method of claim 1 , further comprising performing a manufacturability study by process simulation or wafer verification of the new synthetic via patterns.

11. The computer-implemented method of claim 1 , further comprising:
performing a failure mode analysis on a set of integrated circuits using at least one of the new synthetic via patterns; and
modifying the at least one of the new synthetic via patterns to correct a failure identified by the failure mode analysis.

12. A computer program product for generating synthetic via layout patterns by a coordinate-based Recurrent Neural Network (RNN), the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method comprising:
generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts for a set of integrated circuit elements;
training, by the processor, the coordinate-based RNN with the training data set of coordinate arrays; and
generating, by the processor, using the coordinate-based RNN, new synthetic via patterns.

13. The computer program product of claim 12 , wherein the method further comprises manufacturing an integrated circuit using at least one of the new synthetic via patterns.

14. The computer program product of claim 12 , wherein at least one of the new synthetic via patterns comprises a new pattern relative to the training data set of coordinate arrays.

15. The computer program product of claim 12 , wherein the set of coordinate arrays are used as training data for training the coordinate-based RNN.

16. The computer program product of claim 12 , wherein the coordinate arrays specify the center coordinates of the vias in the set of physical design layouts for the integrated circuit.

17. The computer program product of claim 12 , wherein the method further comprises padding any of coordinate arrays having less than a maximum possible number of vias.

18. The computer program product of claim 12 , wherein the method further comprises performing a design or mask rule checking process on the new synthetic via patterns.

19. The computer program product of claim 12 , wherein the method further comprises converting the new synthetic via patterns having a coordinate basis to another pattern format having a layout basis.

20. A computer processing system for generating synthetic via layout patterns by a coordinate-based Recurrent Neural Network (RNN), the system comprising:
a memory for storing program code; and
a processor, operatively coupled to the memory, for running the program code to
generate a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts for a set of integrated circuit elements;
train the coordinate-based RNN with the training data set of coordinate arrays; and
generate, using the coordinate-based RNN, new synthetic via patterns.

Assignees

• IBM

Inventors

• Sha Jing
• Guillorn Michael A
• Dunn Derren N

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06N3/08 Primary

  Learning methods · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06F17/5081 Primary

  Physics · mapped topic

• G06N3/044

  Recurrent networks, e.g. Hopfield networks · CPC title