Efficient breakpoint detection via caches

Patent metadata

Field	Value
Publication number	US-10599541-B2
Application number	US-201916292646-A
Country	US
Kind code	B2
Filing date	Mar 5, 2019
Priority date	Jan 13, 2017
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

Efficient breakpoint detections via caches comprises monitoring a memory location by detecting cache misses on a cache. Embodiments include identifying a memory address that is to be monitored, storing the memory address in a breakpoint monitoring list, and ensuring that any cache lines overlapping with the memory address are evicted from a cache. Based at least on an indication of an occurrence of a cache miss, embodiments determine whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the breakpoint monitoring list. When the portion of the imported cache line does overlap with the memory address, embodiments process one or more monitoring operations on the memory address, and, based on the memory address being stored in the breakpoint monitoring list, embodiments evict the imported cache line from the cache.

First claim

What is claimed:

1. A method, implemented at a computer system that includes one or more processors, for monitoring a memory location for occurrence of a breakpoint through use of a cache during debugging, the method comprising:
identifying a memory address that is to be monitored;
based at least on identifying the memory address that is to be monitored, performing at least the following:
storing the memory address in a breakpoint monitoring list; and
ensuring that any cache lines overlapping with the memory address are evicted from a cache, including, based on the memory address being stored in the breakpoint monitoring list, evicting one or more cache lines from the cache; and

based at least on an indication of an occurrence of a cache miss, determining whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the breakpoint monitoring list, and when the portion of the imported cache line does overlap with the memory address, performing at least the following:
processing one or more monitoring operations on the memory address, including determining that a breakpoint was encountered when the memory address was written to or read by a memory access operation; and
based on the memory address being stored in the breakpoint monitoring list, evicting the imported cache line from the cache.

2. The method as recited in claim 1 , wherein the one or more monitoring operations include putting at least one of the one or more processors in verbose mode and single-stepping at least one of the one or more processors.

3. The method as recited in claim 1 , wherein determining whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the breakpoint monitoring list comprises determining whether the imported cache line includes a memory address matching the memory address stored in the breakpoint monitoring list.

4. The method as recited in claim 1 , wherein when the portion of the imported cache line does not overlap with the memory address, the imported cache line remains in the cache.

5. The method as recited in claim 1 , further comprising merging cache misses for a plurality of memory operations by performing monitoring operations on a cache line accessed by the plurality of memory operations, while refraining from evicting the cache line during the plurality of memory operations.

6. The method as recited in claim 1 , further comprising merging cache misses for a plurality of memory operations when those memory operations relate to at least one of:
a first breakpoint on a thread's stack, while executing a function owning a stack frame of the thread's stack; or
a second breakpoint within a function, while executing code of the function.

7. A computer system, comprising:
one or more processors; and
one or more hardware storage devices having stored thereon instructions that are executable by the one or more processors to cause the computer system to monitor a memory location for occurrence of a breakpoint through use of a cache during debugging, the instructions including instructions that are executable to cause the computer system to perform at least the following:
identify a memory address that is to be monitored;
based at least on identifying the memory address that is to be monitored, perform at least the following:
store the memory address in a breakpoint monitoring list; and
ensure that any cache lines overlapping with the memory address are evicted from a cache, including, based on the memory address being stored in the breakpoint monitoring list, evicting one or more cache lines from the cache; and

based at least on an indication of an occurrence of a cache miss, determine whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the breakpoint monitoring list, and when the portion of the imported cache line does overlap with the memory address, perform at least the following:
process one or more monitoring operations on the memory address, including determining that a breakpoint was encountered when the memory address was written to or read by a memory access operation; and
based on the memory address being stored in the breakpoint monitoring list, evict the imported cache line from the cache.

8. The computer system as recited in claim 7 , wherein the one or more monitoring operations include putting at least one of the one or more processors in verbose mode and single-stepping at least one of the one or more processors.

9. The computer system as recited in claim 7 , wherein determining whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the breakpoint monitoring list comprises determining whether the imported cache line includes a memory address matching the memory address stored in the breakpoint monitoring list.

10. The computer system as recited in claim 7 , wherein when the portion of the imported cache line does not overlap with the memory address, the imported cache line remains in the cache.

11. The computer system as recited in claim 7 , the instructions including instructions that are executable to cause the computer system to merge cache misses for a plurality of memory operations by performing monitoring operations on a cache line accessed by the plurality of memory operations, while refraining from evicting the cache line during the plurality of memory operations.

12. The computer system as recited in claim 7 , the instructions including instructions that are executable to cause the computer system to merge cache misses for a plurality of memory operations when those memory operations relate to at least one of:
a first breakpoint on a thread's stack, while executing a function owning a stack frame of the thread's stack; or
a second breakpoint within a function, while executing code of the function.

13. A computer program product comprising one or more hardware storage devices having stored thereon instructions that are executable by one or more processors to cause a computer system to monitor a memory location for occurrence of a breakpoint through use of a cache during debugging, the instructions including instructions that are executable to cause the computer system to perform at least the following:
identify a memory address that is to be monitored;
based at least on identifying the memory address that is to be monitored, perform at least the following:
store the memory address in a breakpoint monitoring list; and
ensure that any cache lines overlapping with the memory address are evicted from a cache, including, based on the memory address being stored in the breakpoint monitoring list, evicting one or more cache lines from the cache; and

based at least on an indication of an occurrence of a cache miss, determine whether a portion of a cache line imported into the cache based on the cache miss overlaps with the memory address stored in the breakpoint monitoring list, and when the portion of the imported cache line does overlap with the memory address, perform at least the following:
process one or more monitoring operations on the memory address, including determining that a breakpoint was encountered when the memory address was written to or read by a memory access operation; and
based on the memory address being stored in the breakpoint monitoring list, evict the imported cache line from the cache.

14. The computer program product as recited in claim 13 , wherein the one or more monitoring operations include putting at le

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Mola Jordi

Classifications

• G06F11/3471

  Address tracing · CPC title

• G06F11/3648

  using additional hardware · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F11/362

  Debugging of software · CPC title