Semiconductor device and semiconductor integrated circuit using the same

Patent metadata

Field	Value
Publication number	US-10594265-B2
Application number	US-201816053353-A
Country	US
Kind code	B2
Filing date	Aug 2, 2018
Priority date	Sep 27, 2017
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

A semiconductor device may include an amplification circuit. The amplification circuit may be configured to generate an output signal and an output bar signal based on a mode signal, first and second control signals, an input signal, and an input bar signal. The amplification circuit may determine voltage levels of the output signal and the output bar signal based on the mode signal and the first and second control signals regardless of the input signal and the input bar signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
an amplification circuit configured to generate an output signal and an output bar signal based on a mode signal, first and second control signals, an input signal, and an input bar signal; and
a control circuit configured to generate the first and second control signals based on the mode signal and a reset signal,
wherein the amplification circuit determines voltage levels of the output signal and the output bar signal based on the mode signal and the first and second control signals regardless of the input signal and the input bar signal.

2. The semiconductor device of claim 1 , wherein the control circuit outputs the first and second control signals having substantially a same level or different levels based on the mode signal and the reset signal.

3. The semiconductor device of claim 1 ,
wherein the control circuit outputs the first and second control signals having substantially the same level when the mode signal is enabled, and
wherein the control circuit outputs the first and second control signals having the different levels when the mode signal is disabled.

4. The semiconductor device of claim 1 ,
wherein the control circuit outputs the first and second control signals having a first level when the mode signal is enabled,
wherein the control circuit outputs the first control signal having the first level and the second control signal having a second level when the mode signal is disabled and the reset signal enabled, and
wherein the control circuit outputs the first control signal having the second level and the second control signal having the first level when the mode signal and the reset signal are disabled.

5. The semiconductor device of claim 1 ,
wherein the amplification circuit outputs the output signal and the output bar signal having a second level regardless of the input signal and the input bar signal when the mode signal is enabled and the first and second control signals having a first level are inputted into the amplification circuit,
wherein the amplification circuit outputs the output signal having the second level and the output bar signal having the first level regardless of the input signal and the input bar signal when the mode signal is disabled and the first control signal having the first level and the second control signal having the second level are inputted into the amplification circuit, and
wherein voltage levels of the output signal and the output bar signal are determined based on the input signal and the input bar signal when the mode signal is disabled and the first control signal having the second level and the second control signal having the first level are inputted into the amplification circuit.

6. The semiconductor device of claim 5 , wherein the amplification circuit comprises:
a first input circuit configured to pull-up or pull-down a first output node based on the input signal;
a second input circuit configured to pull-up or pull-down a second output node based on the input bar signal;
a first output signal level determination circuit configured to pull-up or pull-down the first output node based on the second control signal and the mode signal;
a second output signal level determination circuit configured to pull-down the second output node based on the first control signal;
a power block circuit configured to supply or block a voltage to a latch circuit based on the mode signal; and
the latch circuit configured to detect and amplify voltage levels of the first and second output nodes,
wherein the voltage level of the second output node is outputted as the voltage level of the output signal, and the voltage level of the first output node is outputted as the voltage level of the output bar signal.

7. The semiconductor device of claim 6 ,
wherein the first output signal level determination circuit pulls up the first output node when the second control signal has the second level, and
wherein the first output signal level determination circuit pulls down the first output node when the mode signal is enabled.

8. The semiconductor device of claim 6 , wherein the second output signal level determination circuit pulls down the second output node when the first control signal has the first level.

9. A semiconductor integrated circuit comprising:
at least one semiconductor device configured to generate an output signal and an output bar signal based on a mode signal, a reset signal, an input signal, and an input bar signal,
wherein the semiconductor device outputs the output signal and the output bar signal having substantially a same level when the mode signal is enabled,
wherein the semiconductor device outputs the output signal and the output bar signal having different levels based on the reset signal, the input signal, and the input bar signal when the mode signal is disabled, and
wherein the semiconductor device comprises:
a control circuit configured to generate a first control signal and a second control signal based on the mode signal and the reset signal; and
an amplification circuit configured to generate the output signal and the output bar signal based on the mode signal, the first and second control signals, the input signal, and the input bar signal.

10. The semiconductor integrated circuit of claim 9 ,
wherein the control circuit fixes the first and second control signals to a first level regardless of the reset signal when the mode signal is enabled, and
wherein the control circuit fixes the first and second control signals to different levels based on the reset signal when the mode signal is disabled.

11. The semiconductor integrated circuit of claim 9 ,
wherein the control circuit fixes the first control signal to the first level and the second control signal to a second level when the mode signal is disabled and the reset signal is enabled, and
wherein the control circuit fixes the first control signal to the second level and the second control signal to the first level when the mode signal is disabled and the reset signal is disabled.

12. The semiconductor integrated circuit of claim 9 , wherein the amplification circuit comprises:
at least one input circuit configured to pull-up or pull-down first and second output nodes based on the input signal and the input bar signal;
a first output signal level determination circuit configured to pull-up or pull-down the first output node based on the second control signal and the mode signal;
a second output signal level determination circuit configured to pull-down the second output node based on the first control signal;
a latch circuit configured to detect and amplify voltage levels of the first and second output nodes; and
a power block circuit configured to supply or block a voltage to the latch circuit based on the mode signal.

13. A semiconductor device comprising:
a latch circuit configured to detect and amplify voltage levels of first and second output nodes based on an input signal and an input bar signal; and
a power block circuit configured to supply or block an external voltage to the latch circuit based on a mode signal,
wherein the first and second output nodes are pulled-down when the mode signal is enabled.

14. The semiconductor device of claim 13 ,
wherein the power block circuit blocks the external voltage to the latch circuit when the mode signal is enabled, and
wherein the power block circuit supplies the external voltage to the latch circuit when the mode signal is disabled.

15. The semiconductor device of claim 13 , wherein the semiconductor device further comprises:
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Assignees

• Sk Hynix Inc

Inventors

• Hwang Kyu Dong

Classifications

• H03F3/16

  with field-effect devices · CPC title

• H03K3/356026

  with synchronous operation (H03K3/356034, H03K3/356052 take precedence) · CPC title

• H03F2200/87

  the cross coupling circuit being realised only by MOSFETs · CPC title

• H03F1/025 Primary

  by using a signal derived from the input signal · CPC title

• H03F2200/471

  the voltage being sensed · CPC title