Transistors having ultra thin fin profiles and their methods of fabrication

Patent metadata

Field	Value
Publication number	US-10593785-B2
Application number	US-201515771998-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Dec 22, 2015
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.

First claim

We claim:

1. An integrated circuit comprising:
a semiconductor substrate;
an insulation layer formed on the semiconductor substrate, the insulation layer having a top surface; and
a fin extending from the semiconductor substrate, the fin having a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion, the subfin portion disposed in a trench formed in the insulation layer, the subfin portion comprising a III-V semiconductor material and the active fin portion comprising a group IV semiconductor material, wherein the active fin portion has a top active fin portion and a bottom active fin portion, and the top of the active fin portion has a smaller width than the bottom active fin portion, and wherein the bottom active fin portion is above the top surface of the insulation layer.

2. The integrated circuit of claim 1 wherein the III-V semiconductor material is GaAs and wherein the group IV semiconductor material is germanium.

3. The integrated circuit of claim 2 wherein the semiconductor substrate is a monocrystalline silicon substrate.

4. The integrated circuit of claim 1 wherein the active fin portion has a top and sidewalls extending above the insulation layer.

5. The integrated circuit of claim 4 wherein the subfin portion has a top subfin portion and a bottom subfin portion in the trench in the insulation layer wherein the bottom active fin portion is disposed directly on the top of a subfin portion and wherein the bottom active fin portion has a smaller width than the top subfin portion.

6. The integrated circuit of claim 5 wherein the width of the bottom of the subfin portion is greater than the width of the top of the subfin portion.

7. The integrated circuit of claim 1 wherein the subfin further comprises a “V” shaped portion extending into the semiconductor substrate and below the insulation layer.

8. The integrated circuit of claim 1 further comprising a gate structure formed on the active fin portion; and a source region and a drain region disposed on opposite sides of the gate structure.

9. The integrated circuit of claim 8 wherein the gate structure comprises a gate dielectric layer formed on the active fin portion and a gate electrode formed on the gate dielectric layer.

10. The integrated circuit of claim 1 further comprising a second fin extending from the semiconductor substrate, the second fin having a second subfin portion on the semiconductor substrate and a second active fin portion on the second subfin portion, the second subfin portion disposed in a second trench disposed in the insulation layer, the second trench having an aspect ratio (depth to width) of at least 2:1, the second subfin portion comprising the III-V semiconductor material, the second active fin portion comprising a second III-V semiconductor material different than the III-V semiconductor material.

11. A method of forming an integrated circuit comprising:
forming a trench in an insulation layer disposed on a semiconductor substrate, the trench having an aspect ratio of at least 2:1 at the largest width of the trench;
forming a III-V semiconductor material in the trench and above a top surface of the insulation layer;
planarizing the III-V semiconductor material that extends over the trench to a level generally coplanar with the top surface of the insulation layer;
recessing the III-V semiconductor material in the trench so that the III-V semiconductor material has a top surface lower than the top surface of the insulation layer;
forming a group IV semiconductor material on the III-V semiconductor material in the trench and extending above the top surface of the insulation layer;
planarizing the portion of a group IV semiconductor material that extends over the trench to a level generally coplanar with the top surface of the insulation layer;
recessing the insulation layer so that the group IV semiconductor has a top and sidewalls extending above the recessed top surface of the insulation layer to form an active fin portion; and
thinning the sidewalls of the active fin portion to create a thinned active fin portion.

12. The method of forming an integrated circuit of claim 11 wherein the maximum width between the sidewalls of the thinned active fin portion is between 5-50% of the maximum width between the sidewalls of the active fin portion prior to thinning.

13. The method of forming an integrated circuit of claim 11 wherein forming the trench in the insulation layer comprises:
forming a sacrificial fin from the semiconductor substrate;
forming the insulation layer over and around the sacrificial fin;
polishing the insulation layer so that is it substantially planar with the sacrificial fin; and
removing the sacrificial fin to create the trench in the insulation layer.

14. The method of forming an integrated circuit of claim 13 wherein forming the fin comprises etching the semiconductor fin from the semiconductor fin from the semiconductor substrate such that the fin has a top and a bottom wherein the bottom is wider than the top.

15. The method of forming an integrated circuit of claim 11 further comprising forming a gate stack on the top and sidewalls of the thinned active fin portion.

16. The method of forming an integrated circuit of claim 15 wherein forming the gate stack comprises forming a gate dielectric on the top and sidewalls on the thinned active fin region and forming a gate electrode on the gate dielectric layer.

17. The method of forming an integrated circuit of claim 11 further comprising:
after forming the trench in the insulation layer, etching the semiconductor substrate to form a “V” shaped opening in the semiconductor substrate located below the insulation layer.

18. A device comprising: a semiconductor substrate:
an insulation layer disposed on the semiconductor substrate, the insulation layer having a top surface;
a trench disposed in the insulation layer;
a fin having an active fin portion disposed on a subfin portion, the subfin portion having a lower portion formed in a faceted notch in the substrate below the insulation layer and an upper portion disposed in the trench in the insulation layer wherein the width the upper portion of the subfin portion at the bottom of the trench is wider than the width of the upper portion of the subfin at the top of the insulation layer, wherein the subfin portion comprises a III-V semiconductor material and wherein the active fin portion comprises a semiconductor material different from the III-V semiconductor material of the subfin portion, and wherein the active fin portion has a top active fin portion and a bottom active fin portion, and the top of the active fin portion has a smaller width than the bottom active fin portion, and wherein the bottom active fin portion is above the top surface of the insulation layer.

19. The device of claim 18 wherein the III-V semiconductor material of the subfin portion is selected from the group consisting of GaAs and GaAsP, and the semiconductor material of the active fin portion is selected from the group consisting of germanium and SiGe.

20. The device of claim 18 wherein the active fin portion comprises a III-V semiconductor material.

21. The device of claim 18 wherein the active fin portion has a top and sidewalls which extend above the top surface of the insulation layer.

22. The device of claim 18 further comprising a gate stack formed on the active fin portion.

23. An integrated circuit compris

Assignees

• Intel Corp

Inventors

• Gardner Sanaz K
• Rachmady Willy
• Le Van H
• Metz Matthew V
• Kim Seiyon
• Agrawal Ashish
• Kavalieros Jack T

Classifications

• H10P52/402

  of semiconductor materials · CPC title

• H10P50/646

  of Group III-V materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3421

  Arsenides · CPC title

• H10P14/3418

  Phosphides · CPC title