Semiconductor device and method for fabricating the same

US10593777B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10593777-B2
Application numberUS-201816233582-A
CountryUS
Kind codeB2
Filing dateDec 27, 2018
Priority dateJul 13, 2018
Publication dateMar 17, 2020
Grant dateMar 17, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor layer stack comprising: a first conductive layer; a dielectric layer including a high-k material, which is formed on the first conductive layer; a second conductive layer formed on the dielectric layer; and an interface control layer formed between the dielectric layer and the second conductive layer, and including a sequential stack of a leakage blocking material, a dopant material and a high bandgap material, wherein the dopant material is formed between the dielectric layer and the second conductive layer, wherein the leakage blocking material is formed between the dopant material and the dielectric layer, and wherein the high bandgap material is formed between the dopant material and the second conductive layer. 2. The semiconductor layer stack of claim 1 , wherein the interface control layer further includes: a high work function material formed between the high bandgap material and the second conductive layer. 3. The semiconductor layer stack of claim 2 , wherein the high work function material includes a conductive material having a higher work function than the second conductive layer. 4. The semiconductor layer stack of claim 2 , wherein the high work function material includes an intermixed compound of the high bandgap material and the second conductive layer. 5. The semiconductor layer stack of claim 2 , wherein the second conductive layer includes a titanium nitride, the high bandgap material includes an aluminum oxide, and the high work function material includes a titanium aluminum nitride. 6. The semiconductor layer stack of claim 2 , wherein the second conductive layer includes a titanium nitride, the high bandgap material includes a silicon oxide, and the high work function material includes a titanium silicon nitride. 7. The semiconductor layer stack of claim 1 , wherein the dopant material includes a material having a higher dielectric constant than the high-k material and the leakage blocking material. 8. The semiconductor layer stack of claim 1 , wherein each of the high bandgap material and the leakage blocking material includes a material having a higher bandgap than the dopant material. 9. The semiconductor layer stack of claim 1 , wherein the interface control layer includes a multi-layer structure in which the dopant material is formed between the dielectric layer and the second conductive layer, the leakage blocking material is formed between the dopant material and the dielectric layer, and the high bandgap material is formed between the dopant material and the second conductive layer. 10. The semiconductor layer stack of claim 1 , wherein the dopant material includes a dopant that is thermally diffusible to increase a dielectric constant of the dielectric layer. 11. The semiconductor layer stack of claim 1 , wherein each of the dopant material and the high-k material includes a metal oxide, and the dopant material includes a metal oxide having a higher dielectric constant than the high-k material. 12. The semiconductor layer stack of claim 1 , wherein the dopant material includes a titanium oxide. 13. The semiconductor layer stack of claim 1 , wherein each of the high bandgap material and the leakage blocking material includes an aluminum oxide or a silicon oxide. 14. The semiconductor layer stack of claim 1 , wherein the dopant material includes a titanium oxide, and each of the high bandgap material and the leakage blocking material includes an aluminum oxide. 15. The semiconductor layer stack of claim 1 , wherein the dopant material includes a titanium oxide, and each of the high bandgap material and the leakage blocking material includes a silicon oxide. 16. The semiconductor layer stack of claim 1 , wherein each of the high bandgap material and the leakage blocking material is thinner than the dopant material. 17. The semiconductor layer stack of claim 1 , wherein the dielectric layer includes a stack in which a thin high bandgap material is located between a first high-k material and a second high-k material. 18. The semiconductor layer stack of claim 17 , wherein each of the first high-k material and the second high-k material includes a zirconium oxide or a hafnium oxide. 19. The semiconductor layer stack of claim 17 , wherein the thin high bandgap material includes an aluminum oxide or a silicon oxide. 20. The semiconductor layer stack of claim 1 , wherein each of the leakage blocking material, the dopant material and the high bandgap material includes a metal oxide.

Assignees

Inventors

Classifications

  • the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US10593777B2 cover?
A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap mater…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H01L29/517. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 17 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).