System and method for information handling system input/output resource management

Patent metadata

Field	Value
Publication number	US-10592285-B2
Application number	US-201715610218-A
Country	US
Kind code	B2
Filing date	May 31, 2017
Priority date	May 31, 2017
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

An information handling system includes a processor complex with a root complex that provides N serial data lanes, where N is an integer. The information handling system also includes boot process logic that determines that a device is coupled to X of the serial data lanes, where X is an integer less than N, determines that no device is coupled to Y of the serial data lanes, where Y is an integer less than or equal to N−X, and allocates a portion of bus resources of the root complex to the device, the portion being greater (X+Y)/N.

First claim

What is claimed is:

1. An information handling system, comprising:
a processor complex including a Peripheral Component Interconnect-Express (PCIe) root complex that provides N serial data lanes, where N is an integer; and
boot process logic configured to enumerate the root complex during a system boot process for the information handling system, wherein in enumerating the root complex the boot process logic:
determines that a device is coupled to X of the serial data lanes, where X is an integer less than N;
determines that no device is coupled to Y of the serial data lanes, where Y is an integer less than or equal to N−X; and
allocates a portion of bus resources of the root complex to the device, the portion being greater than or equal to (X+Y)/N.

2. The information handling system of claim 1 , wherein N is equal to sixteen.

3. The information handling system of claim 2 , wherein the portion of the bus resources comprise an amount of completion buffer space.

4. The information handling system of claim 3 , wherein the completion buffer space comprises register space within the root complex.

5. The information handling system of claim 3 , wherein the amount of completion buffer space is equal to 512 bytes.

6. The information handling system of claim 2 , wherein the portion of the bus resources comprise a number of outstanding non-posted requests.

7. The information handling system of claim 6 , wherein the number of outstanding non-posted requests is equal to sixteen.

8. The information handling system of claim 1 , wherein the boot process logic comprises a system Basic Input/Output System (BIOS).

9. The information handling system of claim 1 , wherein the boot process logic comprises a system Universal Extensible Firmware Interface (UEFI).

10. A method, comprising:
providing, on a Peripheral Component Interconnect-Express (PCIe) root complex of a processor complex of an information handling system, N serial data lanes, where N is an integer;
determining, by boot process logic of the information handling system configured to enumerate the root complex during a system boot process for the information handling system, that a device is coupled to X of the serial data lanes, where X is an integer less than N;
determining, by the boot process logic, that no device is coupled to Y of the serial data lanes, where Y is an integer less than or equal to N−X; and
allocating, by the boot process logic, a portion of bus resources of the root complex to the device, the portion being greater than or equal to (X+Y)/N.

11. The method of claim 10 , wherein N is equal to sixteen.

12. The method of claim 11 , wherein the portion of the bus resources comprise an amount of completion buffer space.

13. The method of claim 12 , wherein the completion buffer space comprises register space within the root complex.

14. The method of claim 13 , wherein the amount of completion buffer space is equal to 512 bytes.

15. The method of claim 11 , wherein the portion of the bus resources comprise a number of outstanding non-posted requests.

16. The method of claim 15 , wherein the number of outstanding non-posted requests is equal to sixteen.

17. The method of claim 10 , wherein the boot process logic comprises one of a system Basic Input/Output System (BIOS) and a system Universal Extensible Firmware Interface (UEFI).

18. An information handling system, comprising:
a processor complex including a Peripheral Component Interconnect-Express (PCIe) root complex that provides N serial data lanes, where N is an integer; and
boot process logic configured to enumerate the root complex during a system boot process for the information handling system, wherein in enumerating the root complex the boot process logic:
determines that a first device is coupled to X of the serial data lanes, where X is an integer less than N;
allocates a first portion of bus resources to the first device, the first portion being X/N of a total amount of bus resources of the root complex;
determines that a second device is coupled to Y of the serial data lanes, where Y is an integer less than X−N;
determines that no device is coupled to Z of the serial data lanes, where Z is a non-zero integer less than or equal to N−X−Y; and allocates a portion of bus resources of the root complex to the device, the portion being greater than or equal to (Y+Z)/N.

19. The information handling system of claim 18 , wherein the portion of the bus resources comprise an amount of completion buffer space.

20. The information handling system of claim 18 , wherein the portion of the bus resources comprise a number of outstanding non-posted requests.

Assignees

• Dell Products Lp

Inventors

• Beckett John C
• Hormuth Robert W

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F21/575

  Secure boot · CPC title

• G06F21/572

  Secure firmware programming, e.g. of basic input output system [BIOS] · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title