Cache memory with reduced power consumption mode

Patent metadata

Field	Value
Publication number	US-10591978-B2
Application number	US-201715607921-A
Country	US
Kind code	B2
Filing date	May 30, 2017
Priority date	May 30, 2017
Publication date	Mar 17, 2020
Grant date	Mar 17, 2020

Abstract

Processors may include cache circuitry that is a significant source of power consumption. A cache is going to be placed into a lower power mode. Based at least in part on this anticipated transition, the contents of the cache data lines are copied into persistent storage. While the cache is in the lower power mode, the tag circuitry is kept operational. When an access request is made to the cache, a relatively fast lookup of the tag in the tag array can be made. The location where the associated cache line is stored in the persistent storage may be determined from the tag data. Upon a tag hit, the system is able to find the contents of the requested cache line in the persistent storage without returning the storage array of the cache to a fully operational state.

First claim

What is claimed is:

1. An apparatus for processing data, comprising:
a cache memory comprising a storage array and a tag array, the storage array organized into a plurality of cache lines, the tag array providing an index of storage locations associated with data blocks stored in the storage array;
a memory located separate from the cache memory, the apparatus configured to store data stored by the plurality of cache lines in the memory based at least in part on the cache memory being in a reduced power consumption state, the tag array to be operational while the cache memory is in the reduced power consumption state such that locations in the tag array, of the data stored by the plurality of cache lines, are related to corresponding locations in the memory based on the index; and
a controller configured to write data stored by the plurality of cache lines to the memory before the cache memory is placed in the reduced power consumption state, and also configured to, while the cache memory is in the reduced power consumption state, based at least in part on a cache access request for a cache line that was stored by the storage array before the cache memory was placed in the reduced power consumption state, retrieve a data block from the memory that includes the data stored by the cache line prior to the cache memory being placed in the reduced power consumption state.

2. The apparatus of claim 1 , wherein data stored by the plurality of cache lines is to be stored in the memory according to a mapping function that relates the locations in the tag array to the locations in the memory of corresponding cache lines.

3. The apparatus of claim 1 , wherein the controller retrieves, from the memory, the data stored by the cache line before retrieving data previously stored by other cache lines.

4. The apparatus of claim 3 , wherein the mapping function indexes cache memories, ways, and banks therein to locations in the memory.

5. The apparatus of claim 1 , further comprising:
a plurality of last-level caches that can be placed in at least a high power consumption state and the reduced power consumption state, the plurality of last-level caches including the cache memory; and
a plurality of processor cores to access data in the plurality of last-level caches according to a first hashing function that maps processor access addresses to respective ones of the plurality of last-level caches based at least in part on all of the last-level caches being in the first high power consumption state, the plurality of processor cores to access data in the plurality of last-level caches according to a second hashing function that maps processor access addresses to a subset of the plurality of last-level caches based at least in part on at least one of the last-level caches being in the reduced power consumption state.

6. The apparatus of claim 5 , wherein the subset of the plurality of last-level caches does not include the cache memory.

7. A method of operating a cache memory system, comprising:
receiving an indicator that a cache memory in an operable power consumption state is to be placed into a reduced power consumption state, the cache memory organized as a set of cache lines and a set of tag entries, the tag entries providing an index to the cache lines in the cache memory;
based at least in part on the indicator, copying at least a set of valid cache lines from the cache memory to a memory located separate from the cache memory based on the index such that locations in the set of tag entries are related to corresponding location in the memory;
placing the cache memory in the reduced power consumption state, wherein the set of cache lines are not accessed while the cache memory is in the reduced power consumption state;
while the cache memory is in the reduced power consumption state, receiving a cache access request for a cache line;
while the cache memory is in the reduced power consumption state, performing, using the set of tag entries, a tag lookup corresponding to the cache access request; and
based on a result of the tag lookup, determining a location in the memory that corresponds to the cache line and retrieving data at the location in the memory corresponding to the cache line.

8. The method of claim 7 , wherein the result of the tag lookup includes a tag way and tag bank that hold a tag entry corresponding to the cache line.

9. The method of claim 8 , wherein the location in the memory is related to the tag way and tag bank based on a mapping function.

10. The method of claim 9 , further comprising:
based at least in part on a first set of last-level caches of a plurality of last-level caches being in operable power consumption states, mapping, using a first hashing function, accesses by a first processor core of the plurality of processor cores to the first set of last-level caches, the first set of last-level caches including the cache memory; and,
based at least in part on a second set of last-level caches of the plurality of last-level caches being in operable power-consumption states, mapping, using a second hashing function, accesses by the first processor core to the second set of last-level caches, the second set of last-level caches not including the cache memory.

11. A method of operating a processing system, comprising:
receiving, at a cache memory and while the cache memory is in a first power consumption state, a first cache access request corresponding to a cache line stored in a storage array of the cache memory, the cache memory including a tag array providing an index that is used to determine whether the storage array holds the cache line;
before placing the cache memory in a second power consumption state, copying the cache line to an archive memory that is separate from the cache memory;
placing the cache memory in the second power consumption state, the storage array not operable while the cache memory is in the second power consumption state, the tag array being operable while the cache memory is in the second power consumption state such that a location of the cache line in the storage array is related to a corresponding location in the archive memory based on the index;
while the cache memory is in the second power consumption state, receiving a second cache access request corresponding to the cache line; and
based at least in part on the second cache access request, and while the cache memory is in the second power consumption state, determining, using the tag array, the corresponding location of the cache line in the archive memory and retrieving data at the corresponding location of the cache line in the archive memory.

12. The method of claim 11 , wherein the location in the tag array that corresponds to the cache line is mapped to the corresponding location in the archive memory by a mapping function.

13. The method of claim 12 , further comprising:
before copying other cache lines from the archive memory, copying the cache line from the archive memory.

14. The method of claim 12 , further comprising:
placing the cache memory in the first power consumptions state; and,
copying other cache lines from the archive memory to the storage array.

15. The method of claim 14 , wherein the first cache line is copied from the archive memory to provide the cache line based at least in part on the second cache access request.

16. The method of claim 14 , wherein the other cache lines are copied from the archive memory to restore the contents of the storage array.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lai Patrick P
• Shearer Robert Allen

Classifications

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F12/0846

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3243 Primary

  Power saving in microcontroller unit · CPC title